?? jiaotongdeng.txt
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity traffic is
port(clk, reset,urgency: in std_logic;
w1,w2:in std_logic;
r1,r2,y1,y2,g1,g2,c1,c2:out std_logic);
end traffic;
architecture arch of traffic is
type state_space is(s0,s1,s2,s3,s4);
signal state:state_space;
begin
process(clk)
begin
if urgency='1' then
state<=s4;
elsif reset='1' then
state<=s0;
elsif(clk 'event and clk='1')then
case state is
when s0=>
if w1='1' then
state<=s1;
end if;
when s1=>
if w2='1' then
state<=s2;
end if;
when s2=>
if w1='1' then
state<=s3;
end if;
when s3=>
if w2='1' then
state<=s0;
end if;
when s4=>
if urgency='0' then
state<=s0;
end if;
end case;
end if;
end process;
c1<='1' when state=s0 or state=s2 else '0';
c2<='1' when state=s1 or state=s3 else '0';
r1<='1' when state=s0 or state=s1 or state=s4 else '0';
g1<='1' when state=s2 else '0';
y1<='1' when state=s3 else '0';
r2<='1' when state=s2 or state=s3 or state=s4 else '0';
g2<='1' when state=s0 else '0';
y2<='1' when state=s1 else '0';
end arch;
綠燈計數(shù)器:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity lv is
port(
clk:in std_logic;
enable:in std_logic;
c:out std_logic;
a1,a0:buffer std_logic_vector(3 downto 0));
end lv;
architecture lvdeng of lv is
begin
process(clk)
begin
if (clk 'event and clk='1') then
if enable='0' then
a1<="0100";a0<="0000";
elsif a1>0 and a0=0 then
a0<="1001";a1<=a1-"0001";
elsif a0>0 then
a0<=a0-"0001";
end if;
end if;
if a1="0000" and a0="0000" then
c<='1';
else c<='0';
end if;
end process;
end lvdeng;
黃燈計數(shù)器:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity huang is
port(
clk:in std_logic;
enable:in std_logic;
c:out std_logic;
cnt:buffer std_logic_vector(3 downto 0));
end huang;
architecture huangdeng of huang is
begin
process(clk)
begin
if (clk 'event and clk='1') then
if enable='1' and cnt>0 then
cnt<=cnt-"0001";
else cnt<="0100";
end if;
end if;
if cnt=0 then
c<='1';
else c<='0';
end if;
end process;
end huangdeng;
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