IMPORT	osTimer_OIER
	IMPORT	osTimer_OSCR
	IMPORT	osTimer_OSMR3
	IMPORT	osTimer_OSSR
	IMPORT	mem_MSC0
	IMPORT	mem_MSC1
	IMPORT	mem_MSC2
	IMPORT	mem_MDREFR
	IMPORT	mem_MDCNFG
	IMPORT	mem_MDMRS
	IMPORT	pwm_PSSR

	IMPORT	initMem_MSC0
	IMPORT	initMem_MSC1
	IMPORT	initMem_MSC2
	IMPORT	initMem_MDREFR
	IMPORT	initMem_MDCNFG
	IMPORT	initMem_MDMRS

	EXPORT	post_initMem

	AREA post_initMem ,CODE ,READONLY


	ldr r11,=osTimer_OSCR
	ldr r10,=osTimer_OSMR3
	ldr r0,[r11]
	add r0,r0,#0x100000
	str r0,[r10]

	ldr r11,=osTimer_OIER
	mov r0,#0x8
	str r0,[r11]

	ldr r10,=osTimer_OSSR
initMemDelayLoop
	ldr r0,[r10]
	tst r0,#0x8
	beq initMemDelayLoop				;Waiting 200us to ensure the internal SDRAM CLK stable.

	mov r0,#0x0
	str r0,[r11]
	ldr r0,[r10]
	str r0,[r10]					;clear ostimer3 int status

;////////////////
;write the relevant asynchronous static memory Register(MSCn,etc.)
;Write the relevant PCCard Register(MECR,etc.)
;///////////////

	ldr r11,=mem_MDREFR
	ldr r0,[r11]
	orr r0,r0,#0x10000
	str r0,[r11]						;change state to self-refresh

	eor r0,r0,#0x400000
	str r0,[r11]						;change state to pwr down

	orr r0,r0,#0x8000						;change to PWRDWNX
	str r0,[r11]						
	nop
	nop



	ldr r0,=initMem_MDREFR
	str r0,[r11]

	ldr r0,=initMem_MDCNFG
	ldr r11,=mem_MDCNFG
	bic r0,r0,#0x1
	str r0,[r11]						;init mdcnfg&disable sdram partition0

	ldr r11,=pwm_PSSR
	ldr r0,[r11]
	str r0,[r11]


	mov r11,#0x0a0000000
	mov r1,#0x8

postInitSdramRefresh
	ldr r0,[r11]
	sub r1,r1,#0x1
	cmp r1,#0x0
	bne postInitSdramRefresh				;refresh by reading a reserved sdram bank eight twice

	ldr r0,=initMem_MDCNFG
	ldr r11,=mem_MDCNFG
	str r0,[r11]						;enable sdram bank

	ldr r0,=initMem_MDMRS
	ldr r11,=mem_MDMRS
	str r0,[r11]


;////////////////

	ldr r0,=initMem_MSC0
	ldr r11,=mem_MSC0
	str r0,[r11]						;init msc0

	ldr r0,=initMem_MSC1
	ldr r11,=mem_MSC1
	str r0,[r11]


	ldr r0,=initMem_MSC2
	ldr r11,=mem_MSC2
	str r0,[r11]



	mov pc,r14
	END