?? csb_arm_ram_start.s
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/************************************************************************************************************ EXAMPLE CODE** (c) Copyright 2003-2007; Micrium, Inc.; Weston, FL** All rights reserved. Protected by international copyright laws.** Knowledge of the source code may NOT be used to develop a similar product.** Please help us continue to provide the Embedded community with the finest* software available. Your honesty is greatly appreciated.**********************************************************************************************************//************************************************************************************************************ GNU STARTUP FILE** Filename : CSB_ARM_RAM_start.s* Version : V1.89* Programmer(s) : Jean-Denis Hatier**********************************************************************************************************/ /* Mode, correspords to bits 0-5 in CPSR. */ .equ OS_CPU_ARM_MODE_MASK, 0x1F /* Bit mask for mode bits in CPSR */ .equ OS_CPU_ARM_MODE_USR, 0x10 /* User mode */ .equ OS_CPU_ARM_MODE_FIQ, 0x11 /* Fast Interrupt Request mode */ .equ OS_CPU_ARM_MODE_IRQ, 0x12 /* Interrupt Request mode */ .equ OS_CPU_ARM_MODE_SVC, 0x13 /* Supervisor mode */ .equ OS_CPU_ARM_MODE_ABT, 0x17 /* Abort mode */ .equ OS_CPU_ARM_MODE_UND, 0x1B /* Undefined Instruction mode */ .equ OS_CPU_ARM_MODE_SYS, 0x1F /* System mode */ /* Define sizes for each mode's stack. */ .equ OS_CPU_ARM_MODE_FIQ_STK_SIZE, 0x100 .equ OS_CPU_ARM_MODE_IRQ_STK_SIZE, 0x100 .equ OS_CPU_ARM_MODE_ABT_STK_SIZE, 0x100 .equ OS_CPU_ARM_MODE_SVC_STK_SIZE, 0x100 .equ OS_CPU_ARM_MODE_UND_STK_SIZE, 0x100 .equ OS_CPU_ARM_MODE_SYS_STK_SIZE, 0x100 /* Declare the stacks. */ .global OS_CPU_ARM_MODE_FIQ_STK .global OS_CPU_ARM_MODE_IRQ_STK .global OS_CPU_ARM_MODE_ABT_STK .global OS_CPU_ARM_MODE_SVC_STK .global OS_CPU_ARM_MODE_UND_STK .global OS_CPU_ARM_MODE_SYS_STK /* Allocate the stacks, */ .comm OS_CPU_ARM_MODE_FIQ_STK, OS_CPU_ARM_MODE_FIQ_STK_SIZE /* for the FIQ mode, */ .comm OS_CPU_ARM_MODE_IRQ_STK, OS_CPU_ARM_MODE_IRQ_STK_SIZE /* for the IRQ mode, */ .comm OS_CPU_ARM_MODE_ABT_STK, OS_CPU_ARM_MODE_ABT_STK_SIZE /* for the Abort mode, */ .comm OS_CPU_ARM_MODE_SVC_STK, OS_CPU_ARM_MODE_SVC_STK_SIZE /* for the Supervisor mode, */ .comm OS_CPU_ARM_MODE_UND_STK, OS_CPU_ARM_MODE_UND_STK_SIZE /* for the Undef mode, */ .comm OS_CPU_ARM_MODE_SYS_STK, OS_CPU_ARM_MODE_SYS_STK_SIZE /* for the System & User mode. *//************************************************************************************************************************/ .extern _bss .extern _ebss .extern main .global start .section .text /* EXCEPTION TABLE AT ADDRESS 0x00000000. */reset: b start b OS_CPU_ARM_ExceptUndefInstrHndlr b OS_CPU_ARM_ExceptSwiHndlr b OS_CPU_ARM_ExceptPrefetchAbortHndlr b OS_CPU_ARM_ExceptDataAbortHndlr b OS_CPU_ARM_ExceptAddrAbortHndlr b OS_CPU_ARM_ExceptIrqHndlr b OS_CPU_ARM_ExceptFiqHndlrOS_CPU_ARM_ExceptResetHndlr: b OS_CPU_ARM_ExceptResetHndlrOS_CPU_ARM_ExceptUndefInstrHndlr: b OS_CPU_ARM_ExceptUndefInstrHndlrOS_CPU_ARM_ExceptSwiHndlr: b OS_CPU_ARM_ExceptSwiHndlrOS_CPU_ARM_ExceptPrefetchAbortHndlr: b OS_CPU_ARM_ExceptPrefetchAbortHndlrOS_CPU_ARM_ExceptDataAbortHndlr: b OS_CPU_ARM_ExceptDataAbortHndlrOS_CPU_ARM_ExceptAddrAbortHndlr: b OS_CPU_ARM_ExceptAddrAbortHndlrOS_CPU_ARM_ExceptIrqHndlr: b OS_CPU_ARM_ExceptIrqHndlrOS_CPU_ARM_ExceptFiqHndlr: b OS_CPU_ARM_ExceptFiqHndlr/************************************************************************************************************************/ /* At the end of the reset sequence, MMU, ICache, */ /* DCache, and write buffer are all disabled. Also */ /* IRQs and FIQs are disabled in the processor's CPSR. */ /* The operating mode is SYS (system mode), and */ /* the PC is vectored at 0x00000000. A branch in */ /* 0x00000000 brings us directly here. */start: ldr r0, =0x00000000 mcr p15, 0, r0, c3, c0, 0 /* Grant manager access to all domains. */ nop nop nop ldr r0, =0x00002001 mcr p15, 0, r0, c15, c1, 0 /* Allow access to all coprocessors. */ nop nop nop ldr r0, =0x00000000 mcr p15, 0, r0, c8, c7, 0 /* Flush TLB's. */ mcr p15, 0, r0, c7, c7, 0 /* Flush Caches. */ mcr p15, 0, r0, c7, c10, 4 /* Flush Write Buffer. */ nop nop nop /* Disable MMU. */ /* Disable all caches but i-cache. */ /* Disable write buffer. */ /* Change BUS mode to synchronous. */ ldr r0, =0x40001078 mcr p15, 0, r0, c1, c0, 0 nop nop nop /* SET-UP THE STACK-POINTERS FOR ALL OPERATING MODES. */ /* After a reset, the mode is ARM, System, interrupts */ /* disabled. The USR mode uses the same stack as SYS. */ /* The stack segments must be defined in the linker */ /* command file, and be declared above. */ /* FIQ mode. */ mrs r0, cpsr /* Move CPSR to r0. */ bic r0, r0, #OS_CPU_ARM_MODE_MASK /* Clear all mode bits. */ orr r0, r0, #OS_CPU_ARM_MODE_FIQ /* Set FIQ mode bits. */ msr CPSR_c, r0 /* Move back to CPSR. */ /* Initialize the stack ptr. */ ldr sp, =(OS_CPU_ARM_MODE_FIQ_STK + OS_CPU_ARM_MODE_FIQ_STK_SIZE - 4) /* IRQ mode. */ mrs r0, cpsr /* Move CPSR to r0. */ bic r0, r0, #OS_CPU_ARM_MODE_MASK /* Clear all mode bits. */ orr r0, r0, #OS_CPU_ARM_MODE_IRQ /* Set IRQ mode bits. */ msr CPSR_c, r0 /* Move back to CPSR. */ /* Initialize the stack ptr. */ ldr sp, =(OS_CPU_ARM_MODE_IRQ_STK + OS_CPU_ARM_MODE_IRQ_STK_SIZE - 4) /* Abort mode. */ mrs r0, cpsr /* Move CPSR to r0. */ bic r0, r0, #OS_CPU_ARM_MODE_MASK /* Clear all mode bits. */ orr r0, r0, #OS_CPU_ARM_MODE_ABT /* Set Abort mode bits. */ msr CPSR_c, r0 /* Move back to CPSR. */ /* Initialize the stack ptr. */ ldr sp, =(OS_CPU_ARM_MODE_ABT_STK + OS_CPU_ARM_MODE_ABT_STK_SIZE - 4) /* Undef mode. */ mrs r0, cpsr /* Move CPSR to r0. */ bic r0, r0, #OS_CPU_ARM_MODE_MASK /* Clear all mode bits. */ orr r0, r0, #OS_CPU_ARM_MODE_UND /* Set Undef mode bits. */ msr CPSR_c, r0 /* Move back to CPSR. */ /* Initialize the stack ptr. */ ldr sp, =(OS_CPU_ARM_MODE_UND_STK + OS_CPU_ARM_MODE_UND_STK_SIZE - 4) /* System mode. */ mrs r0, cpsr /* Move CPSR to r0. */ bic r0, r0, #OS_CPU_ARM_MODE_MASK /* Clear all mode bits. */ orr r0, r0, #OS_CPU_ARM_MODE_SYS /* Set System mode bits. */ msr CPSR_c, r0 /* Move back to CPSR. */ /* Initialize the stack ptr. */ ldr sp, =(OS_CPU_ARM_MODE_SYS_STK + OS_CPU_ARM_MODE_SYS_STK_SIZE - 4) /* Supervisor mode. */ mrs r0, cpsr /* Move CPSR to r0. */ bic r0, r0, #OS_CPU_ARM_MODE_MASK /* Clear all mode bits. */ orr r0, r0, #OS_CPU_ARM_MODE_SVC /* Set Supervisor mode bits. */ msr CPSR_c, r0 /* Move back to CPSR. */ /* Initialize the stack ptr. */ ldr sp, =(OS_CPU_ARM_MODE_SVC_STK + OS_CPU_ARM_MODE_SVC_STK_SIZE - 4) /* CLEAR BSS. */ ldr r0, =_bss ldr r1, =_ebss mov r2, #0bss_loop: str r2, [r0] add r0, r0, #4 cmp r1, r0 bge bss_loop /* Jump to main(). */ bl main /* The C code should never return. */ b start?? 快捷鍵說(shuō)明
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