?? usbdev.c
字號:
// DbgUsb(("EP_INT_EN_REG : %x \n", Temp));
Outp32(SYS_CON_REG, 0x4023); // error interrupt enable, 16bit bus, Little format, suspend&reset enable
Outp32(EP0_CON_REG, 0x0000);
// EP1 OUT Max Packet size settings
Outp32(INDEX_REG, EP1);
Outp32(EP_CON_REG, 0x0080); // dual enable
// EP2 IN Max Packet size settings
Outp32(INDEX_REG, EP3);
Outp32(EP_CON_REG, 0x0080); // dual enable
Outp32(INDEX_REG, EP0);
}
void HandleEvent(void)
{
U32 uStatus;
U32 Temp,k;
U16 ep_int_status, ep_int;
Inp32(SYS_STATUS_REG, uStatus); // System status read
DbgUsb(("SYS_STATUS_REG : %x \n", uStatus));
if (uStatus & INT_REG_VBUS)
{
Outp32(SYS_STATUS_REG, INT_REG_VBUS); // Interrupt Clear
DbgUsb(("\n [USB_Diag_Log] : INT_REG_VBUS\n"));
}
if (uStatus & 0xfc00) // Error interrupt check
{
Inp32(SYS_STATUS_REG , Temp);
Outp32(SYS_STATUS_REG, INT_ERR); // Interrupt Clear
}
if (uStatus & INT_REG_SUSPEND)
{
Outp32(SYS_STATUS_REG, INT_REG_SUSPEND); // Interrupt Clear
DbgUsb(("\n [USB_Diag_Log] : Suspend Mode"));
}
if (uStatus & INT_REG_RESUME)
{
Outp32(SYS_STATUS_REG, INT_REG_RESUME); // Host software send ClearPortFeature. Interrupt Clear
DbgUsb(("\n [USB_Diag_Log] : Resume Mode \n"));
}
if (uStatus & INT_REG_RESET) // Reset interrupt
{
Outp32(SYS_STATUS_REG, INT_REG_RESET); // Interrupt Clear
SetEndpoint();
g_uEp0State = EP0_STATE_INIT;
DbgUsb(("\n [USB_Diag_Log] : Reset Mode \n"));
}
if (uStatus & INT_REG_SDE) // Device Speed Detection interrupt
{
Outp32(SYS_STATUS_REG, INT_REG_SDE); // Interrupt Clear
DbgUsb(("\n [USB_Diag_Log] : Speed Detection interrupt \n"));
if (uStatus & INT_REG_HSP) // Set if Device is High speed or Full speed
{
Outp32(SYS_STATUS_REG, INT_REG_HSP); // High Speed Device Interrupt Clear?? may be not.
DbgUsb(("\n [USB_Diag_Log] : High Speed Detection\n"));
SetMaxPktSizes(USB_HIGH);
SetDescriptorTable();
}
else
{
SetMaxPktSizes(USB_FULL);
SetDescriptorTable();
}
}
Inp32(TEST_REG, Temp); // EP interrrupt status read
DbgUsb(("TEST_REG : %x \n", Temp));
Inp32(EP_STATUS_REG, ep_int_status); // EP interrrupt status read
DbgUsb(("EP_STATUS_REG : %x \n", ep_int_status));
Inp32(EP_INT_REG, ep_int);
DbgUsb(("EP_INT_REG : %x \n", ep_int));
if (ep_int & INT_REG_EP0)
{
DbgUsb(("\n [USB_Diag_Log] : Control Transfer Interrupt \n"));
Outp32(EP_INT_REG, INT_REG_EP0); // Interrupt Clear
HandleEvent_EP0();
}
// Endpoint1 bulkIn
else if (ep_int & INT_REG_EP1)
{
Outp32(EP_INT_REG, INT_REG_EP1); // Interrupt Clear
HandleEvent_BulkIn();
DbgUsb(("\n [USB_Diag_Log] : Ep1 Interrupt \n"));
}
// Endpoint3 bulkOut
else if (ep_int & INT_REG_EP3)
{
Outp32(EP_INT_REG, INT_REG_EP3); // Interrupt Clear
HandleEvent_BulkOut();
DbgUsb(("\n [USB_Diag_Log] : Bulk Out Transfer Interrupt \n"));
}
}
// ======================================================================
// endpointZeroFunction()
//
// This is function for Control Transfer.
// If it occurs endpoint0 interrupt, this function is called.
// This function check Device Request for Control Transfer type and
// call each other functions.
// ======================================================================
void HandleEvent_EP0(void)
{
//U32 DeviceRequestLength,Temp,k;
U32 Temp,k;
U16 ep0csr;
U16 ReadCnt, i;
U16 ReadBuf[64]={0x0000, };
U8 setaddress;
U32 uRemoteWakeUp;
U32 tmp;
#define TEST_PKT_SIZE 53
#define TEST_ARR_SIZE 54
U8 ahwTestPkt [TEST_ARR_SIZE] = {
0x00,0x00, 0x00,0x00, 0x00,0x00,
0x00,0xAA, 0xAA,0xAA, 0xAA,0xAA, 0xAA,0xAA,
0xAA,0xEE, 0xEE,0xEE, 0xEE,0xEE, 0xEE,0xEE,
0xEE,0xFE, 0xFF,0xFF, 0xFF,0xFF, 0xFF,0xFF,
0xFF,0xFF, 0xFF,0xFF, 0xFF,0x7F, 0xBF,0xDF,
0xEF,0xF7, 0xFB,0xFD, 0xFC,0x7E, 0xBF,0xDF,
0xEF,0xF7, 0xFB,0xFD, 0x7E,0x00, 0x00,0x00
};
Outp32(INDEX_REG, EP0);
Inp32(EP0_STATUS_REG, ep0csr);
// DbgUsb((" Endpoint0 CSR Register = %x \n", ep0csr));
// EP0 CSR register status check
if (ep0csr & EP0_SENT_STALL) // SENT STALL : protocol stall.
{
DbgUsb((" Sent Stall \n"));
Outp32(EP0_STATUS_REG, EP0_SENT_STALL);
if (ep0csr & EP0_RX_SUCCESS)
Outp32(EP0_STATUS_REG, EP0_RX_SUCCESS);
g_uEp0State = EP0_STATE_INIT;
return;
}
if (ep0csr & EP0_TX_SUCCESS)
{
DbgUsb((" EP0_TX_SUCCESS \n"));
Outp32(EP0_STATUS_REG, EP0_TX_SUCCESS);
return;
}
// DbgUsb((" g_uEp0State = %x \n", g_uEp0State));
if(ep0csr & EP0_RX_SUCCESS)
{
if (g_uEp0State == EP0_STATE_INIT)
{
Inp32(BYTE_READ_CNT_REG, ReadCnt);
for(i=0;i<4;i++) Inp32(EP0_FIFO, ReadBuf[i]);
Outp32(EP0_STATUS_REG, EP0_RX_SUCCESS);
g_poDeviceRequest->bmRequestType=ReadBuf[0];
g_poDeviceRequest->bRequest=ReadBuf[0]>>8;
g_poDeviceRequest->wValue_L=ReadBuf[1];
g_poDeviceRequest->wValue_H=ReadBuf[1]>>8;
g_poDeviceRequest->wIndex_L=ReadBuf[2];
g_poDeviceRequest->wIndex_H=ReadBuf[2]>>8;
g_poDeviceRequest->wLength_L=ReadBuf[3];
g_poDeviceRequest->wLength_H=ReadBuf[3]>>8;
PrintEp0Pkt((U8 *)g_poDeviceRequest, 8);
switch (g_poDeviceRequest->bRequest)
{
case STANDARD_SET_ADDRESS:
setaddress = (g_poDeviceRequest->wValue_L); // Set Address Update bit
// DbgUsb(("Func_ADDR_Setaddr : %d \n", setaddress));
Inp32(FUNC_ADDR_REG, tmp);
g_uEp0State = EP0_STATE_INIT;
break;
case STANDARD_SET_DESCRIPTOR:
// DbgUsb(("\n MCU >> Set Descriptor \n"));
break;
case STANDARD_SET_CONFIGURATION:
// DbgUsb(("\n MCU >> Set Configuration \n"));
usConfig = g_poDeviceRequest->wValue_L; // Configuration value in configuration descriptor
g_uEnumerationDone = 1;
/*
if(g_uBulkInCount!=0)
{
g_uBulkInCount+=g_uEp1MaxPktSize;
PrepareEp1Fifo(g_uBulkInAddr-g_uEp1MaxPktSize);
}
*/
break;
case STANDARD_GET_CONFIGURATION:
// Uart_Printf("\n MCU >> Get Configruation \n");
Outp32(BYTE_WRITE_CNT_REG, 1);
Outp32(EP0_FIFO, usConfig);
break;
case STANDARD_GET_DESCRIPTOR:
DeviceRequestLength = (U32)((g_poDeviceRequest->wLength_H << 8) |
g_poDeviceRequest->wLength_L);
switch (g_poDeviceRequest->wValue_H)
{
case DEVICE_DESCRIPTOR:
// DbgUsb(("\n MCU >> Get Device Descriptor \n"));
DeviceRequestLength = (U32)((g_poDeviceRequest->wLength_H << 8) |
g_poDeviceRequest->wLength_L);
g_uEp0State = EP0_STATE_GD_DEV_0_0;
break;
case CONFIGURATION_DESCRIPTOR:
DeviceRequestLength = (U32)((g_poDeviceRequest->wLength_H << 8) |
g_poDeviceRequest->wLength_L);
// DbgUsb(("\n MCU >> Get Configuration Descriptor = %x\n",DeviceRequestLength));
if (DeviceRequestLength > CONFIG_DESC_SIZE){
// === GET_DESCRIPTOR:CONFIGURATION+INTERFACE+ENDPOINT0+ENDPOINT1 ===
// Windows98 gets these 4 descriptors all together by issuing only a request.
// Windows2000 gets each descriptor seperately.
g_uEp0State = EP0_STATE_GD_CFG_0;
}
else
g_uEp0State = EP0_STATE_GD_CFG_ONLY_0; // for win2k
break;
case STRING_DESCRIPTOR :
DeviceRequestLength = (U32)((g_poDeviceRequest->wLength_H << 8) |
g_poDeviceRequest->wLength_L);
switch(g_poDeviceRequest->wValue_L)
{
case 0:
g_uEp0State = EP0_STATE_GD_STR_I0;
break;
case 1:
g_uEp0State = EP0_STATE_GD_STR_I1;
break;
case 2:
g_uEp0State = EP0_STATE_GD_STR_I2;
break;
default:
break;
}
break;
case ENDPOINT_DESCRIPTOR:
switch(g_poDeviceRequest->wValue_L&0xf)
{
case 0:
g_uEp0State=EP0_STATE_GD_EP0_ONLY_0;
break;
case 1:
g_uEp0State=EP0_STATE_GD_EP1_ONLY_0;
break;
default:
break;
}
break;
case DEVICE_QUALIFIER:
DeviceRequestLength = (U32)((g_poDeviceRequest->wLength_H << 8) |
g_poDeviceRequest->wLength_L);
// printf("devicequalify = %d\n",DeviceRequestLength);
if (DeviceRequestLength ==4)
g_uEp0State=EP0_STATE_GD_DEV_QUALIFIER;
else if (DeviceRequestLength ==10)
g_uEp0State=EP0_STATE_GD_DEV_QUALIFIER_1;
break;
case OTHER_SPEED_CONFIGURATION :
DbgUsb(("\n MCU >> Get OTHER_SPEED_CONFIGURATION \n"));
DeviceRequestLength = (U32)((g_poDeviceRequest->wLength_H << 8) |
g_poDeviceRequest->wLength_L);
g_uEp0State = EP0_STATE_GD_DEV_OTHER_SPEED;
break;
default:
break;
}
break;
case STANDARD_CLEAR_FEATURE:
// DbgUsb(("\n MCU >> Clear Feature \n"));
switch (g_poDeviceRequest->bmRequestType)
{
case DEVICE_RECIPIENT:
if (g_poDeviceRequest->wValue_L == 1)
uRemoteWakeUp = FALSE;
break;
case ENDPOINT_RECIPIENT:
if (g_poDeviceRequest->wValue_L == 0)
{
if ((g_poDeviceRequest->wIndex_L & 0x7f) == 0x00)
g_poStatusGet->Endpoint0= 0;
if ((g_poDeviceRequest->wIndex_L & 0x8f) == 0x81) // IN Endpoint 1
g_poStatusGet->Endpoint1= 0;
if ((g_poDeviceRequest->wIndex_L & 0x8f) == 0x03) // OUT Endpoint 3
g_poStatusGet->Endpoint3= 0;
}
break;
default:
break;
}
g_uEp0State = EP0_STATE_INIT;
break;
case STANDARD_SET_FEATURE:
// DbgUsb(("\n MCU >> Set Feature \n"));
switch (g_poDeviceRequest->bmRequestType)
{
case DEVICE_RECIPIENT:
if (g_poDeviceRequest->wValue_L == 1)
uRemoteWakeUp = TRUE;
break;
case ENDPOINT_RECIPIENT:
if (g_poDeviceRequest->wValue_L == 0)
{
if ((g_poDeviceRequest->wIndex_L & 0x7f) == 0x00)
g_poStatusGet->Endpoint0= 1;
if ((g_poDeviceRequest->wIndex_L & 0x8f) == 0x81)
g_poStatusGet->Endpoint1= 1;
if ((g_poDeviceRequest->wIndex_L & 0x8f) == 0x03)
g_poStatusGet->Endpoint3= 1;
}
break;
default:
break;
}
//=======================================================
switch (g_poDeviceRequest->wValue_L) {
case EP_STALL:
// TBD: addnl processing if reqd
break;
case TEST_MODE:
if ((0 != g_poDeviceRequest->wIndex_L ) ||(0 != g_poDeviceRequest->bmRequestType))
break;
// Set TEST MODE
Inp32(TEST_REG,tmp);
tmp|=TR_TMD;
Outp32(TEST_REG,TR_TMD);
switch( g_poDeviceRequest->wIndex_H)
{
case TEST_J:
//Set Test J
Inp32(TEST_REG,tmp);
tmp|=TR_TJS;
Outp32(TEST_REG,tmp);
break;
case TEST_K:
//Set Test K
Inp32(TEST_REG,tmp);
tmp|=TR_TKS;
Outp32(TEST_REG,tmp);
break;
case TEST_SE0_NAK:
//Set Test SE0NAK
Inp32(TEST_REG,tmp);
tmp|=TR_TSNS;
Outp32(TEST_REG,tmp);
break;
case TEST_PACKET:
printf ("Test_packet\n");
Outp32(BYTE_WRITE_CNT_REG, TEST_PKT_SIZE);
WrPktEp0(ahwTestPkt, TEST_PKT_SIZE);
Inp32(TEST_REG,tmp);
tmp|=TR_TPS;
Outp32(TEST_REG,tmp);
printf ("tr=%0X\n", tmp);
break;
}
break;
default:
break;
}
//=======================================================
g_uEp0State = EP0_STATE_INIT;
break;
case STANDARD_GET_STATUS:
switch(g_poDeviceRequest->bmRequestType)
{
case (0x80):
g_poStatusGet->Device=((U8)uRemoteWakeUp<<1)|0x1; // SelfPowered
g_uEp0State = EP0_GET_STATUS0;
break;
case (0x81):
g_poStatusGet->Interface=0;
g_uEp0State = EP0_GET_STATUS1;
break;
case (0x82):
if ((g_poDeviceRequest->wIndex_L & 0x7f) == 0x00)
g_uEp0State = EP0_GET_STATUS2;
if ((g_poDeviceRequest->wIndex_L & 0x8f) == 0x81)
g_uEp0State = EP0_GET_STATUS3;
if ((g_poDeviceRequest->wIndex_L & 0x8f) == 0x03)
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