;/**
;* Project Name : S3C2450 verification project
;*
;* Copyright 2004 by Samsung Electronics, Inc.
;* All rights reserved.
;*
;* Project Description :
;* This software is only for verifying functions of the S3C2450. 
;* Anybody can use this code without our permission.
;*/

;/**
;* File Name    : startup.s
;* Description  : S3C2450 startup code
;* Author       : GOM
;* Dept         : Mobile solution, AP
;* Created Date : 2008.02.22
;* Version      : 0.0
;* History
;*/

				GET		Option.inc
				GET		2450addr.inc

				MACRO
$HandlerLabel 	HANDLER		$HandleLabel

$HandlerLabel
				sub		sp,sp,#4        	;decrement sp(to store jump address)
				stmfd	sp!,{r0}        	;PUSH the work register to stack(lr doesnt push because it return to original address)
				ldr     r0,=$HandleLabel	;load the address of HandleXXX to r0
				ldr     r0,[r0]         	;load the contents(service routine start address) of HandleXXX
				str     r0,[sp,#4]      	;store the contents(ISR) of HandleXXX to stack
				ldmfd   sp!,{r0,pc}     	;POP the work register and pc(jump to ISR)

				MEND


				;IMPORT	MMU_SetAsyncBusMode
				IMPORT	InitMEM
				IMPORT	InitSSMC	

				IMPORT  __main   			; The main entry of mon program 

				AREA    Init,CODE,READONLY

				ENTRY 

				b		ResetHandler	;handler for Reset  
				b		HandlerUndef	;handler for Undefined mode
				b		HandlerSWI		;handler for SWI interrupt
				b		HandlerPabort	;handler for PAbort
				b		HandlerDabort	;handler for DAbort
				b		.				;reserved
			    b		HandlerIRQ		;handler for IRQ interrupt 
				b		HandlerFIQ		;handler for FIQ interrupt
	
HandlerUndef	HANDLER HandleUndef
HandlerSWI		HANDLER HandleSWI
HandlerPabort	HANDLER HandlePabort
HandlerDabort	HANDLER HandleDabort
HandlerIRQ		HANDLER HandleIRQ
HandlerFIQ		HANDLER	HandleFIQ


;=======================================================
;						ENTRY  
;=======================================================

ResetHandler	; edited by junon 060522

				ldr		r0,=WTCON			;	Disable WatchDog.
				mov		r1,#0
				str		r1,[r0]			

				ldr		r0,=CLKDIV0			;	Set Clock Divider
				ldr		r1,[r0]
				bic		r1,r1,#0x37		; clear HCLKDIV, PREDIV, PCLKDIV
				bic		r1,r1,#(0xf<<9) ; clear ARMCLKDIV
				ldr		r2,=((Startup_ARMCLKdiv<<9)|(Startup_PREdiv<<4)|(1<<3)|(Startup_PCLKdiv<<2)|(Startup_HCLKdiv)) 
				orr		r1,r1,r2
				str		r1,[r0]			

				ldr		r0,=LOCKCON0		;	Set lock time of MPLL. added by junon
				mov		r1,#0xe10			;	Fin = 12MHz - 0xE10
				str		r1,[r0]				
	
				ldr		r0,=MPLLCON			;	Set MPLL on
				ldr		r1,=((0<<24)|(Startup_Mdiv<<14)|(Startup_Pdiv<<5)|(Startup_Sdiv))
				str		r1,[r0]			

				ldr		r0,=CLKSRC			;	Select MPLL clock out for SYSCLK
				ldr		r1,[r0]
				orr		r1,r1,#0x10
				str		r1,[r0]		
				
				;bl		MMU_SetAsyncBusMode

				bl		InitMEM
				bl		InitSSMC				
				

			   	bl		__main
			   	b		.

				LTORG


			   	ALIGN

			   	AREA IntVector, DATA, READWRITE

				^   _ISR_STARTADDRESS

HandleReset 	#   4
HandleUndef 	#   4
HandleSWI   	#   4
HandlePabort    #   4
HandleDabort    #   4
HandleReserved  #   4
HandleIRQ   	#   4
HandleFIQ   	#   4

		        END