/********************************************************************************
* 
*	Project Name : S3C6400 Validation
*
*	Copyright 2006 by Samsung Electronics, Inc.
*	All rights reserved.
*
*	Project Description :
*		This software is only for verifying functions of the S3C6400.
*		Anybody can use this software without our permission.
*  
*--------------------------------------------------------------------------------
* 
*	File Name : PCM_test.c
*	File Description :
*
*	Author	: Yoh-Han Lee
*	Dept. : AP Development Team
*
*	Version : 0.2
* 
*	History
*	- Version 0.1 (2007/03/16)
*	  -> Available with AK2440 PCM Codec.
*   - Version 0.2 (2007/04/19)
*     -> Also, working with WM8753 PCM Codec.
*
********************************************************************************/

#ifndef __PCM_H__
#define __PCM_H__
 
#include "codec.h" 
  
#ifdef __cplusplus
extern "C" {
#endif

///////////////////////////////////////////////////////////////
#define PCM_REC_BUF  				0x31000000
//#define PCM_REC_LEN 				0xfffff
#define PCM_REC_LEN 				(8000*2*10)//bytes  8KHz mono 16bit 10sec

#define PCM_SCLK_EN				(1<<19)
#define PCM_PCM_ENABLE			(1<<0)
#define PCM_RXFIFO_EN   			(1<<1)
#define PCM_TXFIFO_EN			(1<<2)
#define RX_MSB_POS0				(0<<3)
#define RX_MSB_POS1				(1<<3)
#define TX_MSB_POS0				(0<<4)
#define TX_MSB_POS1				(1<<4)
#define PCM_RX_DMA_EN			(1<<5)
#define PCM_TX_DMA_EN			(1<<6)
#define RXFIFO_DIPSTICK(n)		(((n)&0x3f) <<7)
#define TXFIFO_DIPSTICK(n)		(((n)&0x3f) <<13)

///////////////////////////////////////////////////////////////////////////////////////

//FPGA IO B'd 
#define INVERTED_R194_DEFAULT					0
#define NORMAL_R196_BOARDCHANGED				1
#define AUDIOPORT1_SEL	NORMAL_R196_BOARDCHANGED


// Codec Master CLK ON/OFF
#define OFF							0
#define ON							1
#define PCM_CODEC_MASTERCLK		ON

//External CLK
//#define EXT_CLOCK_FREQ			25000000		
#define EXT_CLOCK_FREQ_B_16_9344	16934400		
#define EXT_CLOCK_FREQ_A_32_768		32768000
#define EXT_CLOCK_FREQ_A_36_864		36864000

//#define EXT_CLOCK_FREQ_A_32_768		12000000


// PCM CODEC NAME 
//#define PCM_CODEC_NAME			WM9713
#define PCM_CODEC_NAME			PCM_WM8753
//PCM_PORT;
#define PCM_PORT0	0
#define PCM_PORT1 	1

//play mode
#define PCM_POLLING		0
#define PCM_INTERRUPT	1
#define PCM_DMA			2

//PCM_CLKSRC;
#define PCM_PCMCDCLK	0
#define PCM_PCLK		1

//PCM_SCLK
#define SCLK_128K 	128000
#define SCLK_256K 	256000
#define SCLK_512K 	512000
#define SCLK_768K 	768000
#define SCLK_1536K 	1536000

//PCM_SYNC_CLK;
#define SYNC_8K 	8000
#define SYNC_16K	16000
#define SYNC_32K	32000
#define SYNC_48K	48000
#define SYNC_64K	64000
#define SYNC_96K	96000

#define SYNC_11025	11025
#define SYNC_22050	22050
#define SYNC_44100	44100
#define SYNC_88200	88200


//PCM_MSBPOS;
#define DURING_PCMSYNC_HIGH	0
#define AFTER_PCMSYNC_HIGH	1

//PCM_Configuration;
#define Init	0
#define Set		1


///////////////////////////////////////////
// STATUS registers
//

//PCM_CTRL
#define RXFIFO_DIPSTICK0			( (rPCM_CTL0>>7) & 0x3f )
#define TXFIFO_DIPSTICK0			( (rPCM_CTL0>>13) & 0x3f )

#define RXFIFO_DIPSTICK1			( (rPCM_CTL1>>7) & 0x3f )
#define TXFIFO_DIPSTICK1			( (rPCM_CTL1>>13) & 0x3f )


//PCM_FIFO(//1)
#define FIFO_TXFIFO_COUNT			( (rPCM_FIFO_STAT1>>14) & 0x3f )
#define FIFO_RXFIFO_COUNT			( (rPCM_FIFO_STAT1>>4) & 0x3f )

#define FIFO_TXFIFO_COUNT0			( (rPCM_FIFO_STAT0>>14) & 0x3f )
#define FIFO_RXFIFO_COUNT0			( (rPCM_FIFO_STAT0>>4) & 0x3f )

#define FIFO_TXFIFO_COUNT1			( (rPCM_FIFO_STAT1>>14) & 0x3f )
#define FIFO_RXFIFO_COUNT1			( (rPCM_FIFO_STAT1>>4) & 0x3f )

///////////////////////////////////////////
// CONTROL registers
//

//PCM_FIFO
#define FIFO_TXFIFO_EMPTY			(1<<13)
#define FIFO_TXFIFO_ALMOST_EMPTY	(1<<12)
#define FIFO_TXFIFO_FULL			(1<<11)
#define FIFO_TXFIFO_ALMOST_FULL		(1<<10)



#define FIFO_RXFIFO_EMPTY			(1<<3)
#define FIFO_RXFIFO_ALMOST_EMPTY	(1<<2)
#define FIFO_RXFIFO_FULL			(1<<1)
#define FIFO_RXFIFO_ALMOST_FULL		(1<<0)


//PCM_INT
#define EN_IRQ_TO_ARM		(1<<14)//ctrl
#define IRQ_PENDING			(1<<13)//stat
#define TRANSFER_DONE		(1<<12)

#define TXFIFO_EMPTY		(1<<11)
#define TXFIFO_ALMOST_EMPTY	(1<<10)
#define TXFIFO_FULL			(1<<9)
#define TXFIFO_ALMOST_FULL		(1<<8)
#define TXFIFO_ERROR_STARVE		(1<<7)
#define TXFIFO_ERROR_OVERFLOW	(1<<6)

#define RXFIFO_EMPTY			(1<<5)
#define RXFIFO_ALMOST_EMPTY		(1<<4)
#define RXFIFO_FULL			(1<<3)
#define RXFIFO_ALMOST_FULL		(1<<2)
#define RXFIFO_ERROR_STARVE		(1<<1)
#define RXFIFO_ERROR_OVERFLOW	(1<<0)

#define CLRINT	(1<<0)//clrint
///////////////////////////////////////////////////////////////////////////////////////

/*
typedef struct
{
	u32 m_uNumDma;
	DMASELECT_eID m_eDmaId;
	DMA_UNIT m_eDmaUnit;
	DMA_CH m_eDmaCh;
	u32 m_uPcmRxFifoAddr;
	u32 m_uPcmTxFifoAddr;
	DREQ_SRC m_eDreqSrc;
	u32 m_uNumInt;	
}PCM;
*/

typedef struct
{
	unsigned char		CodecID;
	unsigned char		PCMPort;
		
	unsigned char		PCMClkSrc;
	unsigned int 		EXTCDCLKFreq;
	unsigned int		PCMSync;
	unsigned int		PCMSClk;	
	
	unsigned char 		PCMMSBPosition;	
	
	unsigned char 		Playmode;//0.polling 1. interrupt 2. dma
}PCM_State;

typedef struct
{
	unsigned int 	irqstat1;//before clearint
	unsigned int 	irqstat2;//after clearint	
}PCM_IRQstat;
#define PCM_IRQ_STAT_MAX	20
///////////////////////////////////////////////////////////////////////////////////////

void Test_PCM(void);

void PCM_Init(void);
void PCM_AUTO_set(PCM_State setting);


void PCM_SelectPort(void);
	void PCM_SetPort(unsigned char ePort);
void PCM_SelectPCMCLKSOURCE(void);
void PCM_SelectPCMSYNC_SCLK(void);
void PCM_SelectSyncPosition(void);



void PCM_SelClkSrc(unsigned char ePort, unsigned char eClkSrc, bool enable);

void PCM_CodecExitPCMIn(void);
bool PCM_CodecInitPCMIn(unsigned int eSync, unsigned char eMSBPos, unsigned int eSclk, unsigned char eClkSrc);
void PCM_CodecExitPCMOut(void);
bool PCM_CodecInitPCMOut(unsigned int eSync, unsigned char eMSBPos, unsigned int eSclk, unsigned char eClkSrc);


bool PCM_PCMInDMA(unsigned int uRecBufferAddr, unsigned int uPcmSize, bool (*fn_extra)(void));
bool PCM_PCMOutDMA(unsigned int uRecBufferAddr, unsigned int uPcmSize, bool (*fn_extra)(void));

void PCM_PCMInInt(unsigned int uRecBufferAddr, unsigned int uPcmSize);
void PCM_PCMOutInt(unsigned int uRecBufferAddr, unsigned int uPcmSize);

void PCM_PCMOutInt2(unsigned int uBufferAddr, unsigned int uPcmSize);

void PCM_ClearInt(void);
void PCM_EnableInt(void);
void PCM_DisableInt(void);
void PCM_SetInt(unsigned int ePcmInt);

//extra bit by bit test
void PCM_pcmtest4(void);

bool PCM_GetClkValAndClkDir(unsigned int* uSclkDiv, unsigned int* uSyncDiv);


void PCM_ISRInit(void);
void PCM_ISRDeInit(void);
void __irq Isr_PCM_Interrupt(void);
void __irq Isr_PCM_InterruptTEST(void);
void __irq Isr_PCM_PCMIn_DMADone(void);
void __irq Isr_PCM_PCMOut_DMADone(void);
void __irq Isr_PCM_PCMIn(void);
void __irq Isr_PCM_PCMOut(void);
void __irq Isr_PCM_PCMOut2(void);


//void PCM_WM8753MasterCLKGen(unsigned char ePort);



#ifdef __cplusplus
}
#endif

#endif /*__PCM_H__*/