#include <p33FJ64GP306.h>

_FOSCSEL(FNOSC_PRIPLL);			// Primary (XT, HS, EC) Oscillator with PLL

_FOSC(FCKSM_CSDCMD & OSCIOFNC_OFF  & POSCMD_EC);  
								// Clock Switching and Fail Safe Clock Monitor is disabled
								// OSC2 Pin Function: OSC2 is Clock Output
								// Primary Oscillator Mode: EC, External
								
_FWDT(FWDTEN_OFF);              // Watchdog Timer Enabled/disabled by user software
								// (LPRC can be disabled by clearing SWDTEN bit in RCON register


void init_cpu(void)
{

// Configure Oscillator to operate the device at 67.73MHz
// Fosc= Fin*M/(N1*N2), Fcy=Fosc/2
// Fosc= 11.288M*24/(2*2)=67.728MHz
// Fcy, Instruction Clock = Fosc/2 = 33.864MHz

	PLLFBD=22;					// M=24
	CLKDIVbits.PLLPOST=0;		// N1=2
	CLKDIVbits.PLLPRE=0;		// N2=2
	
// Disable Watch Dog Timer
    RCONbits.SWDTEN=0;

// Wait for PLL to lock
	while(OSCCONbits.LOCK!=1) {};
	
}