/* * Intracom TI6711/TI6412 DSP */#include <common.h>#include <post.h>#include "mpc8xx.h"struct ram_range {	u32 start;	u32 size;};#if defined(CONFIG_NETTA_6412)static const struct ram_range int_ram[] = {	{ 0x00000000U, 0x00040000U },};static const struct ram_range ext_ram[] = {	{ 0x80000000U, 0x00100000U },};static const struct ram_range ranges[] = {	{ 0x00000000U, 0x00040000U },	{ 0x80000000U, 0x00100000U },};static inline u16 bit_invert(u16 d){	register u8 i;	register u16 r;	register u16 bit;	r = 0;	for (i = 0; i < 16; i++) {		bit = d & (1 << i);		if (bit != 0)			r |= 1 << (15 - i);	}	return r;}#elsestatic const struct ram_range int_ram[] = {	{ 0x00000000U, 0x00010000U },};static const struct ram_range ext_ram[] = {	{ 0x80000000U, 0x00100000U },};static const struct ram_range ranges[] = {	{ 0x00000000U, 0x00010000U },	{ 0x80000000U, 0x00100000U },};#endif/*******************************************************************************************************/static inline int addr_in_int_ram(u32 addr){	int i;	for (i = 0; i < sizeof(int_ram)/sizeof(int_ram[0]); i++)		if (addr >= int_ram[i].start && addr < int_ram[i].start + int_ram[i].size)			return 1;	return 0;}static inline int addr_in_ext_ram(u32 addr){	int i;	for (i = 0; i < sizeof(ext_ram)/sizeof(ext_ram[0]); i++)		if (addr >= ext_ram[i].start && addr < ext_ram[i].start + ext_ram[i].size)			return 1;	return 0;}/*******************************************************************************************************/#define DSP_HPIC	0x0#define DSP_HPIA	0x4#define DSP_HPID1	0x8#define DSP_HPID2	0xCstatic u32 dummy_delay;static volatile u32 *ti6711_delay = &dummy_delay;static inline void dsp_go_slow(void){	volatile memctl8xx_t *memctl = &((immap_t *)CFG_IMMR)->im_memctl;#if defined(CONFIG_NETTA_6412)	memctl->memc_or6 |= OR_SCY_15_CLK | OR_TRLX;#else	memctl->memc_or2 |= OR_SCY_15_CLK | OR_TRLX;#endif	memctl->memc_or5 |= OR_SCY_15_CLK | OR_TRLX;	ti6711_delay = (u32 *)DUMMY_BASE;}static inline void dsp_go_fast(void){	volatile memctl8xx_t *memctl = &((immap_t *)CFG_IMMR)->im_memctl;#if defined(CONFIG_NETTA_6412)	memctl->memc_or6 = (memctl->memc_or6 & ~(OR_SCY_15_CLK | OR_TRLX)) | OR_SCY_0_CLK;#else	memctl->memc_or2 = (memctl->memc_or2 & ~(OR_SCY_15_CLK | OR_TRLX)) | OR_SCY_3_CLK;#endif	memctl->memc_or5 = (memctl->memc_or5 & ~(OR_SCY_15_CLK | OR_TRLX)) | OR_SCY_0_CLK;	ti6711_delay = &dummy_delay;}/*******************************************************************************************************/static inline void dsp_delay(void){	/* perform ti6711_delay chip select read to have a small delay */	(void) *(volatile u32 *)ti6711_delay;}static inline u16 dsp_read_hpic(void){#if defined(CONFIG_NETTA_6412)	return bit_invert(*((volatile u16 *)DSP_BASE));#else	return *((volatile u16 *)DSP_BASE);#endif}static inline void dsp_write_hpic(u16 val){#if defined(CONFIG_NETTA_6412)	*((volatile u16 *)DSP_BASE) = bit_invert(val);#else	*((volatile u16 *)DSP_BASE) = val;#endif}static inline void dsp_reset(void){#if defined(CONFIG_NETTA_6412)	((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat &= ~(1 << (15 - 15));	udelay(500);	((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat |=  (1 << (15 - 15));	udelay(500);#else	((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat &= ~(1 << (15 - 7));	udelay(250);	((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat |=  (1 << (15 - 7));	udelay(250);#endif}static inline u32 dsp_read_hpic_word(u32 addr){	u32 val;	volatile u16 *p;#if defined(CONFIG_NETTA_6412)	p = (volatile u16 *)((volatile u8 *)DSP_BASE + addr);	val = ((u32) bit_invert(p[0]) << 16);	/* dsp_delay(); */	val |= bit_invert(p[1]);	/* dsp_delay(); */#else	p = (volatile u16 *)((volatile u8 *)DSP_BASE + addr);	val = ((u32) p[0] << 16);	dsp_delay();	val |= p[1];	dsp_delay();#endif	return val;}static inline u16 dsp_read_hpic_hi_hword(u32 addr){#if defined(CONFIG_NETTA_6412)	return bit_invert(*(volatile u16 *)((volatile u8 *)DSP_BASE + addr));#else	return *(volatile u16 *)((volatile u8 *)DSP_BASE + addr);#endif}static inline u16 dsp_read_hpic_lo_hword(u32 addr){#if defined(CONFIG_NETTA_6412)	return bit_invert(*(volatile u16 *)((volatile u8 *)DSP_BASE + addr + 2));#else	return *(volatile u16 *)((volatile u8 *)DSP_BASE + addr + 2);#endif}static inline void dsp_wait_hrdy(void){	int i;	i = 0;#if defined(CONFIG_NETTA_6412)	while (i < 1000 && (dsp_read_hpic_word(DSP_HPIC) & 0x08) == 0) {#else	while (i < 1000 && (dsp_read_hpic() & 0x08) == 0) {#endif		dsp_delay();		i++;	}}static inline void dsp_write_hpic_word(u32 addr, u32 val){	volatile u16 *p;#if defined(CONFIG_NETTA_6412)	p = (volatile u16 *)((volatile u8 *)DSP_BASE + addr);	p[0] = bit_invert((u16)(val >> 16));	/* dsp_delay(); */	p[1] = bit_invert((u16)val);	/* dsp_delay(); */#else	p = (volatile u16 *)((volatile u8 *)DSP_BASE + addr);	p[0] = (u16)(val >> 16);	dsp_delay();	p[1] = (u16)val;	dsp_delay();#endif}static inline void dsp_write_hpic_hi_hword(u32 addr, u16 val_h){#if defined(CONFIG_NETTA_6412)	*(volatile u16 *)((volatile u8 *)DSP_BASE + addr) = bit_invert(val_h);#else	*(volatile u16 *)((volatile u8 *)DSP_BASE + addr) = val_h;#endif}static inline void dsp_write_hpic_lo_hword(u32 addr, u16 val_l){#if defined(CONFIG_NETTA_6412)	*(volatile u16 *)((volatile u8 *)DSP_BASE + addr + 2) = bit_invert(val_l);#else	*(volatile u16 *)((volatile u8 *)DSP_BASE + addr + 2) = val_l;#endif}/********************************************************************/static inline void c62_write_word(u32 addr, u32 val){	dsp_write_hpic_hi_hword(DSP_HPIA, (u16)(addr >> 16));#if !defined(CONFIG_NETTA_6412)	dsp_delay();#endif	dsp_write_hpic_lo_hword(DSP_HPIA, (u16)addr);#if !defined(CONFIG_NETTA_6412)	dsp_delay();#endif	dsp_wait_hrdy();#if !defined(CONFIG_NETTA_6412)	dsp_delay();#endif	dsp_write_hpic_hi_hword(DSP_HPID2, (u16)(val >> 16));#if !defined(CONFIG_NETTA_6412)	dsp_delay();	/* dsp_wait_hrdy();	dsp_delay(); */#endif	dsp_write_hpic_lo_hword(DSP_HPID2, (u16)val);#if !defined(CONFIG_NETTA_6412)	dsp_delay();#endif}static u32 c62_read_word(u32 addr){	u32 val;	dsp_write_hpic_hi_hword(DSP_HPIA, (u16)(addr >> 16));#if !defined(CONFIG_NETTA_6412)	dsp_delay();#endif	dsp_write_hpic_lo_hword(DSP_HPIA, (u16)addr);#if !defined(CONFIG_NETTA_6412)	dsp_delay();#endif	/* FETCH */#if defined(CONFIG_NETTA_6412)