LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY SH057 IS 
PORT(clk2,cp,dir,free: IN STD_LOGIC;
     clr:IN STD_LOGIC;
     comp_a,comp_b:IN STD_LOGIC;     
     phase_a,phase_b: OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
     elc_a,elc_b:OUT STD_LOGIC_VECTOR(5 DOWNTO 0));
END SH057; 

ARCHITECTURE microstep_2 OF SH057 IS 
 SIGNAL sw_a,sw_b:STD_LOGIC_VECTOR(1 DOWNTO 0);
 SIGNAL reg_sw_a,reg_sw_b:STD_LOGIC_VECTOR(1 DOWNTO 0);
 SIGNAL a_h,b_h:STD_LOGIC_VECTOR(1 DOWNTO 0); 
 SIGNAL buf_a_h,buf_b_h:STD_LOGIC_VECTOR(1 DOWNTO 0); 
 SIGNAL buf_elc_a,buf_elc_b:STD_LOGIC_VECTOR(5 DOWNTO 0);
 SIGNAL reset_elc_a,reset_elc_b:STD_LOGIC_VECTOR(5 DOWNTO 0);
 SIGNAL buf_bf:STD_LOGIC;
 
 BEGIN 

 PROCESS(clr,buf_elc_a,buf_elc_b,buf_a_h,buf_b_h)
   BEGIN    
    if clr='1' then 
      elc_a<=buf_elc_a;
      elc_b<=buf_elc_b;
      a_h<=buf_a_h;
      b_h<=buf_b_h;
    else    
      elc_a<="000000";
      elc_b<="111111";
      a_h<="00";
      b_h<="10";
     end if;   
  END PROCESS;
 
elc_dis:PROCESS(cp,dir,free) 
   VARIABLE state_elc: INTEGER RANGE 0 TO 3:=0; 
   VARIABLE state_h:INTEGER RANGE 0 TO 7:=0;  
   BEGIN 
     IF clr='1' THEN
      IF free='1' THEN        
       IF cp'EVENT AND cp='0' THEN             
         IF dir='0' THEN 
            IF state_h=7 THEN state_h:=0; 
              ELSE state_h:=state_h+1;
            END IF;       
            IF state_elc=3 THEN state_elc:=0;                   
              ELSE state_elc:=state_elc+1;
            END IF;
         ELSE 
            IF state_h=0 THEN state_h:=7;
              ELSE state_h:=state_h-1;
            END IF;
            IF state_elc=0 THEN state_elc:=3;                   
              ELSE state_elc:=state_elc-1;
            END IF;                    
         END IF;               
        CASE state_elc IS
            WHEN 0 => buf_elc_a<="000000";buf_elc_b<="111111";
            WHEN 1 => buf_elc_a<="101101";buf_elc_b<="101101";
            WHEN 2 => buf_elc_a<="111111";buf_elc_b<="000000";
            WHEN 3 => buf_elc_a<="101101";buf_elc_b<="101101";
        END CASE;
      END IF;     
        CASE state_h IS
            WHEN 0 => buf_a_h<="00";buf_b_h<="10";
            WHEN 1 => buf_a_h<="01";buf_b_h<="10";
            WHEN 2 => buf_a_h<="01";buf_b_h<="00";
            WHEN 3 => buf_a_h<="01";buf_b_h<="01";
            WHEN 4 => buf_a_h<="00";buf_b_h<="01";
            WHEN 5 => buf_a_h<="10";buf_b_h<="01";
            WHEN 6 => buf_a_h<="10";buf_b_h<="00";
            WHEN 7 => buf_a_h<="10";buf_b_h<="10";
         END CASE;             
       ELSE buf_a_h<="00";buf_b_h<="00";             
      END IF;
    END IF;         
  END PROCESS;

PROCESS(clk2,comp_a,a_h)
variable  bf_a:STD_LOGIC:='0';
  BEGIN
  IF comp_a='1' then 
   IF clk2='1' then phase_a<=a_h;bf_a:='1';
     elsif clk2='0' then if bf_a='1' then phase_a<=a_h; else phase_a<="00";end if;                 
       end if ;
      else phase_a<="00";bf_a:='0'; 
    END IF;
  END PROCESS; 

PROCESS(clk2,comp_b,b_h)
variable  bf_b:STD_LOGIC:='0';
  BEGIN
  IF comp_a='1' then 
   IF clk2='1' then phase_b<=b_h;bf_b:='1';
     elsif clk2='0' then if bf_b='1' then phase_b<=b_h; else phase_b<="00";end if;                 
       end if ;
      else phase_b<="00";bf_b:='0'; 
    END IF;
  END PROCESS; 
       
END microstep_2;