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<title>
Documentation of VHDL-AMS models
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<td class="Title" width="802" colspan="2">Charge pump test bench
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Model Name
</td><td class="SectionText" width="700">
<model_name>BENCH(TEST_DPLL)</model_name>
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Description
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<description>The test-bench shows how a digital PLL is built up from<br>a phase-frequency detector, a charge pump, an integrator<br>and a VCO.<br>
</description>
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Dependencies
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Logical Library
</td><td class="TableHeader">
Design Unit/Design Entity
</td>
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<td class="TableText">IEEE_proposed
</td><td class="TableText">ELECTRICAL_SYSTEMS
</td>
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<td class="TableText">IEEE
</td><td class="TableText">MATH_REAL
</td>
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<td class="TableText">WORK
</td><td class="TableText">VCO(ANALOG)
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<td class="TableText">WORK
</td><td class="TableText">CP(SIMPLE)
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<td class="TableText">WORK
</td><td class="TableText">PFD(A1)
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Source
</td><td class="SectionText" width="700"><A HREF="../bench.vhd">See source code</A> </td>
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Results
</td><td class="SectionText" width="700"><A HREF="bench.jpg">See results</A></td>
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