?? ioat90usb1287.h
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/****** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** */
/****** Created: 2005-11-29 12:56 ******* Source: AT90USB1287.xml ********* */
/**************************************************************************
*
* - File Name : "ioAT90USB1287.h"
* - Title : Register/Bit Definitions for the AT90USB1287
* - Date : 2005-11-29
* - Version : 2.20
* - Support E-Mail : avr@atmel.com
* - Target MCU : AT90USB1287
*
* - Compiler : GNU AVRGCC
*
**************************************************************************
*/
#ifndef _IOAT90USB1287_H_
#define _IOAT90USB1287_H_
/* ***** SPECIFY DEVICE *************************************************** */
#define PART_NAME AT90USB1287
#define SIGNATURE_000 0x1e
#define SIGNATURE_001 0x97
#define SIGNATURE_002 0x82
/* ***** I/O REGISTER DEFINITIONS ***************************************** */
/* NOTE:
* Definitions marked "MEMORY MAPPED"are extended I/O ports
* and cannot be used with IN/OUT instructions
*/
#define PLLCSR _SFR_IO8(0x29)
#define TESTPADSTATUS _SFR_MEM8(0xfd)
#define TESTPADPULL _SFR_MEM8(0xfe)
#define TESTPADCTRL _SFR_MEM8(0xff)
#define UPERRX _SFR_MEM8(0xf5)
#define UEINT _SFR_MEM8(0xf4)
#define UPINT _SFR_MEM8(0xf8)
#define UEBCHX _SFR_MEM8(0xf3)
#define UPBCHX _SFR_MEM8(0xf7)
#define UEBCLX _SFR_MEM8(0xf2)
#define UPBCLX _SFR_MEM8(0xf6)
#define UEDATX _SFR_MEM8(0xf1)
#define UPDATX _SFR_MEM8(0xaf)
#define UEIENX _SFR_MEM8(0xf0)
#define UPIENX _SFR_MEM8(0xae)
#define UESTA1X _SFR_MEM8(0xef)
#define UPCFG2X _SFR_MEM8(0xad)
#define UESTA0X _SFR_MEM8(0xee)
#define UPSTAX _SFR_MEM8(0xac)
#define UECFG1X _SFR_MEM8(0xed)
#define UPCFG1X _SFR_MEM8(0xab)
#define UECFG0X _SFR_MEM8(0xec)
#define UPCFG0X _SFR_MEM8(0xaa)
#define UECONX _SFR_MEM8(0xeb)
#define UPCONX _SFR_MEM8(0xa9)
#define UERST _SFR_MEM8(0xea)
#define UPRST _SFR_MEM8(0xa8)
#define UENUM _SFR_MEM8(0xe9)
#define UPNUM _SFR_MEM8(0xa7)
#define UEINTX _SFR_MEM8(0xe8)
#define UPINTX _SFR_MEM8(0xa6)
#define UDTST _SFR_MEM8(0xe7)
#define UPINRQX _SFR_MEM8(0xa5)
#define UDMFN _SFR_MEM8(0xe6)
#define UHFLEN _SFR_MEM8(0xa4)
#define UDFNUMH _SFR_MEM8(0xe5)
#define UHFNUMH _SFR_MEM8(0xa3)
#define UDFNUML _SFR_MEM8(0xe4)
#define UHFNUML _SFR_MEM8(0xa2)
#define UDADDR _SFR_MEM8(0xe3)
#define UHADDR _SFR_MEM8(0xa1)
#define UDIEN _SFR_MEM8(0xe2)
#define UHIEN _SFR_MEM8(0xa0)
#define UDINT _SFR_MEM8(0xe1)
#define UHINT _SFR_MEM8(0x9f)
#define UDCON _SFR_MEM8(0xe0)
#define UHCON _SFR_MEM8(0x9e)
#define OTGINT _SFR_MEM8(0xdf)
#define OTGIEN _SFR_MEM8(0xde)
#define OTGCON _SFR_MEM8(0xdd)
#define OTGTCON _SFR_MEM8(0xf9)
#define UDPADDH _SFR_MEM8(0xdc)
#define UDPADDL _SFR_MEM8(0xdb)
#define USBINT _SFR_MEM8(0xda)
#define USBSTA _SFR_MEM8(0xd9)
#define USBCON _SFR_MEM8(0xd8)
#define UHWCON _SFR_MEM8(0xd7)
#define UCSR2B _SFR_MEM8(0xd1)
#define UCSR2A _SFR_MEM8(0xd0)
#define UDR1 _SFR_MEM8(0xce)
#define UBRR1 _SFR_MEM16(0xcc)
#define UCSR1C _SFR_MEM8(0xca)
#define UCSR1B _SFR_MEM8(0xc9)
#define UCSR1A _SFR_MEM8(0xc8)
#define TWAMR _SFR_MEM8(0xbd)
#define TWCR _SFR_MEM8(0xbc)
#define TWDR _SFR_MEM8(0xbb)
#define TWAR _SFR_MEM8(0xba)
#define TWSR _SFR_MEM8(0xb9)
#define TWBR _SFR_MEM8(0xb8)
#define ASSR _SFR_MEM8(0xb6)
#define OCR2B _SFR_MEM8(0xb4)
#define OCR2A _SFR_MEM8(0xb3)
#define TCNT2 _SFR_MEM8(0xb2)
#define TCCR2B _SFR_MEM8(0xb1)
#define TCCR2A _SFR_MEM8(0xb0)
#define OCR4CH _SFR_MEM8(0xad)
#define OCR4CL _SFR_MEM8(0xac)
#define OCR4BH _SFR_MEM8(0xab)
#define OCR4BL _SFR_MEM8(0xaa)
#define OCR4AH _SFR_MEM8(0xa9)
#define OCR4AL _SFR_MEM8(0xa8)
#define ICR4H _SFR_MEM8(0xa7)
#define ICR4L _SFR_MEM8(0xa6)
#define TCNT4H _SFR_MEM8(0xa5)
#define TCNT4L _SFR_MEM8(0xa4)
#define TCCR4C _SFR_MEM8(0xa2)
#define TCCR4B _SFR_MEM8(0xa1)
#define TCCR4A _SFR_MEM8(0xa0)
#define OCR3C _SFR_MEM16(0x9c)
#define OCR3B _SFR_MEM16(0x9a)
#define OCR3A _SFR_MEM16(0x98)
#define ICR3 _SFR_MEM16(0x96)
#define TCNT3 _SFR_MEM16(0x94)
#define TCCR3C _SFR_MEM8(0x92)
#define TCCR3B _SFR_MEM8(0x91)
#define TCCR3A _SFR_MEM8(0x90)
#define OCR1C _SFR_MEM16(0x8c)
#define OCR1B _SFR_MEM16(0x8a)
#define OCR1A _SFR_MEM16(0x88)
#define ICR1 _SFR_MEM16(0x86)
#define TCNT1 _SFR_MEM16(0x84)
#define TCCR1C _SFR_MEM8(0x82)
#define TCCR1B _SFR_MEM8(0x81)
#define TCCR1A _SFR_MEM8(0x80)
#define DIDR1 _SFR_MEM8(0x7f)
#define DIDR0 _SFR_MEM8(0x7e)
#define DIDR2 _SFR_MEM8(0x7d)
#define ADMUX _SFR_MEM8(0x7c)
#define ADCSRB _SFR_MEM8(0x7b)
#define ADCSRA _SFR_MEM8(0x7a)
#define ADCH _SFR_MEM8(0x79)
#define ADCL _SFR_MEM8(0x78)
#define XMCRB _SFR_MEM8(0x75)
#define XMCRA _SFR_MEM8(0x74)
#define TIMSK5 _SFR_MEM8(0x73)
#define TIMSK4 _SFR_MEM8(0x72)
#define TIMSK3 _SFR_MEM8(0x71)
#define TIMSK2 _SFR_MEM8(0x70)
#define TIMSK1 _SFR_MEM8(0x6f)
#define TIMSK0 _SFR_MEM8(0x6e)
#define PCMSK2 _SFR_MEM8(0x6d)
#define PCMSK1 _SFR_MEM8(0x6c)
#define PCMSK0 _SFR_MEM8(0x6b)
#define EICRB _SFR_MEM8(0x6a)
#define EICRA _SFR_MEM8(0x69)
#define PCICR _SFR_MEM8(0x68)
#define OSCCAL _SFR_MEM8(0x66)
#define PRR1 _SFR_MEM8(0x65)
#define PRR0 _SFR_MEM8(0x64)
#define CLKPR _SFR_MEM8(0x61)
#define WDTCSR _SFR_MEM8(0x60)
#define SREG _SFR_IO8(0x3f)
#define SP _SFR_IO16(0x3d)
#define EIND _SFR_IO8(0x3c)
#define RAMPZ _SFR_IO8(0x3b)
#define SPMCSR _SFR_IO8(0x37)
#define MCUCR _SFR_IO8(0x35)
#define MCUSR _SFR_IO8(0x34)
#define SMCR _SFR_IO8(0x33)
#define OCDR _SFR_IO8(0x31)
#define ACSR _SFR_IO8(0x30)
#define SPDR _SFR_IO8(0x2e)
#define SPSR _SFR_IO8(0x2d)
#define SPCR _SFR_IO8(0x2c)
#define GPIOR2 _SFR_IO8(0x2b)
#define GPIOR1 _SFR_IO8(0x2a)
#define OCR0B _SFR_IO8(0x28)
#define OCR0A _SFR_IO8(0x27)
#define TCNT0 _SFR_IO8(0x26)
#define TCCR0B _SFR_IO8(0x25)
#define TCCR0A _SFR_IO8(0x24)
#define GTCCR _SFR_IO8(0x23)
#define EEARH _SFR_IO8(0x22)
#define EEARL _SFR_IO8(0x21)
#define EEDR _SFR_IO8(0x20)
#define EECR _SFR_IO8(0x1f)
#define GPIOR0 _SFR_IO8(0x1e)
#define EIMSK _SFR_IO8(0x1d)
#define EIFR _SFR_IO8(0x1c)
#define PCIFR _SFR_IO8(0x1b)
#define TIFR5 _SFR_IO8(0x1a)
#define TIFR4 _SFR_IO8(0x19)
#define TIFR3 _SFR_IO8(0x18)
#define TIFR2 _SFR_IO8(0x17)
#define TIFR1 _SFR_IO8(0x16)
#define TIFR0 _SFR_IO8(0x15)
#define PORTF _SFR_IO8(0x11)
#define DDRF _SFR_IO8(0x10)
#define PINF _SFR_IO8(0x0f)
#define PORTE _SFR_IO8(0x0e)
#define DDRE _SFR_IO8(0x0d)
#define PINE _SFR_IO8(0x0c)
#define PORTD _SFR_IO8(0x0b)
#define DDRD _SFR_IO8(0x0a)
#define PIND _SFR_IO8(0x09)
#define PORTC _SFR_IO8(0x08)
#define DDRC _SFR_IO8(0x07)
#define PINC _SFR_IO8(0x06)
#define PORTB _SFR_IO8(0x05)
#define DDRB _SFR_IO8(0x04)
#define PINB _SFR_IO8(0x03)
#define PORTA _SFR_IO8(0x02)
#define DDRA _SFR_IO8(0x01)
#define PINA _SFR_IO8(0x00)
/* ***** BIT DEFINITIONS ************************************************** */
#define CLKPCE 7
/* ***** WATCHDOG ********************* */
/* WDTCSR - Watchdog Timer Control Register */
#define WDP0 0 // Watch Dog Timer Prescaler bit 0
#define WDP1 1 // Watch Dog Timer Prescaler bit 1
#define WDP2 2 // Watch Dog Timer Prescaler bit 2
#define WDE 3 // Watch Dog Enable
#define WDCE 4 // Watchdog Change Enable
#define WDP3 5 // Watchdog Timer Prescaler Bit 3
#define WDIE 6 // Watchdog Timeout Interrupt Enable
#define WDIF 7 // Watchdog Timeout Interrupt Flag
/* ***** PORTA ************************ */
/* PORTA - Port A Data Register */
#define PORTA0 0 // Port A Data Register bit 0
#define PORTA1 1 // Port A Data Register bit 1
#define PORTA2 2 // Port A Data Register bit 2
#define PORTA3 3 // Port A Data Register bit 3
#define PORTA4 4 // Port A Data Register bit 4
#define PORTA5 5 // Port A Data Register bit 5
#define PORTA6 6 // Port A Data Register bit 6
#define PORTA7 7 // Port A Data Register bit 7
/* DDRA - Port A Data Direction Register */
#define DDA0 0 // Data Direction Register, Port A, bit 0
#define DDA1 1 // Data Direction Register, Port A, bit 1
#define DDA2 2 // Data Direction Register, Port A, bit 2
#define DDA3 3 // Data Direction Register, Port A, bit 3
#define DDA4 4 // Data Direction Register, Port A, bit 4
#define DDA5 5 // Data Direction Register, Port A, bit 5
#define DDA6 6 // Data Direction Register, Port A, bit 6
#define DDA7 7 // Data Direction Register, Port A, bit 7
/* PINA - Port A Input Pins */
#define PINA0 0 // Input Pins, Port A bit 0
#define PINA1 1 // Input Pins, Port A bit 1
#define PINA2 2 // Input Pins, Port A bit 2
#define PINA3 3 // Input Pins, Port A bit 3
#define PINA4 4 // Input Pins, Port A bit 4
#define PINA5 5 // Input Pins, Port A bit 5
#define PINA6 6 // Input Pins, Port A bit 6
#define PINA7 7 // Input Pins, Port A bit 7
/* ***** PORTB ************************ */
/* PORTB - Port B Data Register */
#define PORTB0 0 // Port B Data Register bit 0
#define PORTB1 1 // Port B Data Register bit 1
#define PORTB2 2 // Port B Data Register bit 2
#define PORTB3 3 // Port B Data Register bit 3
#define PORTB4 4 // Port B Data Register bit 4
#define PORTB5 5 // Port B Data Register bit 5
#define PORTB6 6 // Port B Data Register bit 6
#define PORTB7 7 // Port B Data Register bit 7
/* DDRB - Port B Data Direction Register */
#define DDB0 0 // Port B Data Direction Register bit 0
#define DDB1 1 // Port B Data Direction Register bit 1
#define DDB2 2 // Port B Data Direction Register bit 2
#define DDB3 3 // Port B Data Direction Register bit 3
#define DDB4 4 // Port B Data Direction Register bit 4
#define DDB5 5 // Port B Data Direction Register bit 5
#define DDB6 6 // Port B Data Direction Register bit 6
#define DDB7 7 // Port B Data Direction Register bit 7
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