#Build: Synplify 9.4A1, Build 169R, Jun 11 2008
#install: D:\Actel\Libero\Libero_v8.4\Synplify\synplify_94A1
#OS:  6.0
#Hostname: LUAIN-PC

#Implementation: synthesis

#Mon Nov 24 22:04:42 2008

$ Start of Compile
#Mon Nov 24 22:04:42 2008

Synplicity Verilog Compiler, version 1.0, Build 061R, built Jun 30 2008
Copyright (C) 1994-2008, Synplicity Inc.  All Rights Reserved

@I::"D:\Actel\Libero\Libero_v8.4\Synplify\synplify_94A1\lib\proasic\proasic3.v"
@I::"D:\Actelprj\Static_PLL\hdl\ctrl_PLL.v"
@I::"D:\Actelprj\Static_PLL\smartgen\PLL_0P75M\PLL_0P75M.v"
@I::"D:\Actelprj\Static_PLL\hdl\PLL_top.v"
Verilog syntax check successful!
Selecting top level module PLL_top
@N: CG364 :"D:\Actelprj\Static_PLL\hdl\ctrl_PLL.v":8:7:8:14|Synthesizing module ctrl_PLL

@N: CG364 :"D:\Actel\Libero\Libero_v8.4\Synplify\synplify_94A1\lib\proasic\proasic3.v":1864:7:1864:9|Synthesizing module VCC

@N: CG364 :"D:\Actel\Libero\Libero_v8.4\Synplify\synplify_94A1\lib\proasic\proasic3.v":1163:7:1163:9|Synthesizing module GND

@N: CG364 :"D:\Actel\Libero\Libero_v8.4\Synplify\synplify_94A1\lib\proasic\proasic3.v":2447:7:2447:9|Synthesizing module PLL

@N: CG364 :"D:\Actel\Libero\Libero_v8.4\Synplify\synplify_94A1\lib\proasic\proasic3.v":276:7:276:12|Synthesizing module PLLINT

@N: CG364 :"D:\Actelprj\Static_PLL\smartgen\PLL_0P75M\PLL_0P75M.v":5:7:5:15|Synthesizing module PLL_0P75M

@E: CS168 :"D:\Actelprj\Static_PLL\smartgen\PLL_0P75M\PLL_0P75M.v":17:60:17:60|port OADIVHALF does not exist
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Mon Nov 24 22:04:43 2008

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