?? ehci.c
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/**
* ehci.c - USB driver stack project for Windows NT 4.0
*
* Copyright (c) 2002-2004 Zhiming mypublic99@yahoo.com
*
* This program/include file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published
* by the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program/include file is distributed in the hope that it will be
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along with
* this program (in the main directory of the distribution, the file
* COPYING); if not, write to the Free Software Foundation,Inc., 59 Temple
* Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include "usbdriver.h"
#include "ehci.h"
//----------------------------------------------------------
// ehci routines
//#define DEMO
#define DEFAULT_ENDP( enDP ) \
( enDP->flags & USB_ENDP_FLAG_DEFAULT_ENDP )
#define dev_from_endp( enDP ) \
( DEFAULT_ENDP( enDP )\
? ( ( PUSB_DEV )( enDP )->pusb_if )\
: ( ( enDP )->pusb_if->pusb_config->pusb_dev ) )
#define endp_state( enDP ) ( ( enDP )->flags & USB_ENDP_FLAG_STAT_MASK )
#define endp_num( enDP ) \
( DEFAULT_ENDP( enDP )\
? 0 \
: ( ( enDP )->pusb_endp_desc->bEndpointAddress & 0x0f ) )
#define endp_dir( enDP ) \
( DEFAULT_ENDP( enDP )\
? 0L\
: ( ( enDP )->pusb_endp_desc->bEndpointAddress & USB_DIR_IN ) )
#define dev_set_state( pdEV, staTE ) \
( pdEV->flags = ( ( pdEV )->flags & ( ~USB_DEV_STATE_MASK ) ) | ( staTE ) )
#define endp_max_packet_size( enDP ) \
( DEFAULT_ENDP( enDP )\
? ( ( ( PUSB_DEV )enDP->pusb_if )->pusb_dev_desc ? \
( ( PUSB_DEV )enDP->pusb_if )->pusb_dev_desc->bMaxPacketSize0\
: 8 )\
: ( enDP->pusb_endp_desc->wMaxPacketSize & 0x7ff ) )
#define endp_mult_count( endp ) ( ( ( endp->pusb_endp_desc->wMaxPacketSize & 0x1800 ) >> 11 ) + 1 )
#if 0
/* WTF?! */
#define release_adapter( padapTER ) \
{\
( ( padapTER ) ); \
}
#else
#define release_adapter( padapTER ) (void)(padapTER)
#endif
#define get_int_idx( _urb, _idx ) \
{\
UCHAR interVAL;\
interVAL = ( UCHAR )( ( _urb )->pipe >> 24 );\
for( _idx = 1; _idx < 9; _idx++ )\
{\
interVAL >>= 1;\
if( !interVAL )\
break;\
}\
_idx --;\
}
#define ehci_insert_urb_to_schedule( eHCI, pURB, rET ) \
{\
SYNC_PARAM sync_param;\
sync_param.ehci = eHCI;\
sync_param.context = ( pURB );\
sync_param.ret = FALSE;\
\
rET = KeSynchronizeExecution( eHCI->pdev_ext->ehci_int, ehci_sync_insert_urb_schedule, &sync_param );\
}
#define EHCI_ERROR_INT ( STS_FATAL | STS_ERR )
#define EHCI_QH_ERROR( qh_contENT ) ( ( qh_contENT )->cur_qtd.status & ( QTD_STS_HALT | QTD_STS_DBE | QTD_STS_BABBLE | QTD_STS_XACT | QTD_STS_MMF ) )
#define EHCI_QTD_ERROR( qtd_contENT ) ( ( qtd_contENT )->status & ( QTD_STS_HALT | QTD_STS_DBE | QTD_STS_BABBLE | QTD_STS_XACT | QTD_STS_MMF ) )
#define EHCI_READ_PORT_ULONG( pul ) ( *pul )
#define EHCI_WRITE_PORT_ULONG( pul, src ) \
{\
ULONG cmd_reg;\
*pul = ( ULONG )src;\
cmd_reg = EHCI_READ_PORT_ULONG( ehci->port_base + EHCI_USBCMD );\
if( cmd_reg == 0 )\
cmd_reg++;\
}
#define EHCI_READ_PORT_UCHAR( pch ) ( *pch )
#define EHCI_WRITE_PORT_UCHAR( pch, src ) ( *pch = ( UCHAR )src )
#define EHCI_READ_PORT_USHORT( psh ) ( *psh )
#define EHCI_WRITE_PORT_USHORT( psh, src ) ( *psh = ( USHORT )src )
#define press_doorbell( eHCI ) \
{\
ULONG tmp;\
tmp = EHCI_READ_PORT_ULONG( ( PULONG )( ( eHCI )->port_base + EHCI_USBCMD ) );\
tmp |= CMD_IAAD;\
EHCI_WRITE_PORT_ULONG( ( PULONG )( ( eHCI )->port_base + EHCI_USBCMD ), tmp );\
}
#define ehci_from_hcd( hCD ) ( struct_ptr( ( hCD ), EHCI_DEV, hcd_interf ) )
#define qh_from_list_entry( pentry ) ( ( PEHCI_QH )( ( ( ULONG )struct_ptr( pentry, EHCI_ELEM_LINKS, elem_link )->phys_part ) & PHYS_PART_ADDR_MASK ) )
#define qtd_from_list_entry( pentry ) ( ( PEHCI_QTD )( ( ( ULONG )struct_ptr( pentry, EHCI_ELEM_LINKS, elem_link )->phys_part ) & PHYS_PART_ADDR_MASK ) )
#define itd_from_list_entry( pentry ) ( ( PEHCI_ITD )( ( ( ULONG )struct_ptr( pentry, EHCI_ELEM_LINKS, elem_link )->phys_part ) & PHYS_PART_ADDR_MASK ) )
#define sitd_from_list_entry( pentry ) ( ( PEHCI_SITD )( ( ( ULONG )struct_ptr( pentry, EHCI_ELEM_LINKS, elem_link )->phys_part ) & PHYS_PART_ADDR_MASK ) )
#define fstn_from_list_entry( pentry ) ( ( PEHCI_FSTN )( ( ( ULONG )struct_ptr( pentry, EHCI_ELEM_LINKS, elem_link )->phys_part ) & PHYS_PART_ADDR_MASK ) )
#define qh_from_schedule( pentry ) ( ( PEHCI_QH )( ( ( ULONG )struct_ptr( pentry, EHCI_ELEM_LINKS, sched_link )->phys_part ) & PHYS_PART_ADDR_MASK ) )
#define itd_from_schedule( pentry ) ( ( PEHCI_ITD )( ( ( ULONG )struct_ptr( pentry, EHCI_ELEM_LINKS, sched_link )->phys_part ) & PHYS_PART_ADDR_MASK ) )
#define sitd_from_schedule( pentry ) ( ( PEHCI_SITD )( ( ( ULONG )struct_ptr( pentry, EHCI_ELEM_LINKS, sched_link )->phys_part ) & PHYS_PART_ADDR_MASK ) )
#define fstn_from_schedule( pentry ) ( ( PEHCI_FSTN )( ( ( ULONG )struct_ptr( pentry, EHCI_ELEM_LINKS, sched_link )->phys_part ) & PHYS_PART_ADDR_MASK ) )
#define elem_type( ptr, from_list ) ( from_list ? ( ( ( ( ULONG )struct_ptr( ptr, EHCI_ELEM_LINKS, elem_link)->phys_part ) & PHYS_PART_TYPE_MASK ) >> 1 ) \
: ( ( ( ( ULONG )struct_ptr( ptr, EHCI_ELEM_LINKS, sched_link)->phys_part ) & PHYS_PART_TYPE_MASK ) >> 1 ) )
// #define elem_type_list_entry( pentry ) ( ( qh_from_schedule( pentry )->hw_next & 0x06 ) >> 1 )
#define elem_type_list_entry( pentry ) ( elem_type( pentry, TRUE ) )
#define get_parent_hs_hub( pDEV, parent_HUB, port_IDX ) \
{\
parent_HUB = pDEV->parent_dev;\
port_IDX = pdev->port_idx;\
while( parent_HUB )\
{\
if( ( parent_HUB->flags & USB_DEV_CLASS_MASK ) != USB_DEV_CLASS_HUB )\
{\
parent_HUB = NULL;\
break;\
}\
if( ( parent_HUB->flags & USB_DEV_FLAG_HIGH_SPEED ) == 0 )\
{\
port_IDX = parent_HUB->port_idx;\
parent_HUB = parent_HUB->parent_dev;\
continue;\
}\
break;\
}\
}
#define init_elem_phys_part( pelnk ) RtlZeroMemory( ( PVOID )( ( ( ULONG )( pelnk )->phys_part ) & PHYS_PART_ADDR_MASK ), get_elem_phys_part_size( ( ( ( ULONG )( pelnk )->phys_part ) & 0x06 ) >> 1 ) )
#define REAL_INTERVAL ( 1 << pipe_content->interval )
#define elem_safe_free( ptHIS, single ) \
{\
UCHAR em_type; \
em_type = ( UCHAR )elem_type( ptHIS, TRUE ); \
if( ptHIS )\
{\
if( em_type == INIT_LIST_FLAG_QTD )\
{\
elem_pool_lock( qtd_pool, TRUE );\
if( single )\
elem_pool_free_elem( qtd_from_list_entry( ptHIS )->elem_head_link );\
else \
elem_pool_free_elems( qtd_from_list_entry( ptHIS )->elem_head_link );\
elem_pool_unlock( qtd_pool, TRUE );\
}\
else if( em_type == INIT_LIST_FLAG_ITD )\
{\
elem_pool_lock( itd_pool, TRUE );\
if( single )\
elem_pool_free_elem( itd_from_list_entry( ptHIS )->elem_head_link );\
else \
elem_pool_free_elems( itd_from_list_entry( ptHIS )->elem_head_link );\
elem_pool_unlock( itd_pool, TRUE );\
}\
else if( em_type == INIT_LIST_FLAG_SITD )\
{\
elem_pool_lock( sitd_pool, TRUE );\
if( single )\
elem_pool_free_elem( sitd_from_list_entry( ptHIS )->elem_head_link );\
else \
elem_pool_free_elems( sitd_from_list_entry( ptHIS )->elem_head_link );\
elem_pool_unlock( sitd_pool, TRUE );\
}\
else if( em_type == INIT_LIST_FLAG_FSTN )\
{\
elem_pool_lock( fstn_pool, TRUE );\
if( single )\
elem_pool_free_elem( fstn_from_list_entry( ptHIS )->elem_head_link );\
else \
elem_pool_free_elems( fstn_from_list_entry( ptHIS )->elem_head_link );\
elem_pool_unlock( fstn_pool, TRUE );\
}\
else if( em_type == INIT_LIST_FLAG_QH )\
{\
elem_pool_lock( qh_pool, TRUE );\
if( single )\
elem_pool_free_elem( qh_from_list_entry( ptHIS )->elem_head_link );\
else \
elem_pool_free_elems( qh_from_list_entry( ptHIS )->elem_head_link );\
elem_pool_unlock( qh_pool, TRUE );\
}\
}\
}
#ifndef min
#define min( a, b ) ( ( a ) > ( b ) ? ( b ) : ( a ) )
#endif
#ifndef max
#define max( a, b ) ( ( a ) > ( b ) ? ( a ) : ( b ) )
#endif
#define CLR_RH2_PORTSTAT( port_idx, x ) \
{\
PULONG addr; \
addr = ( PULONG )( ehci->port_base + port_idx ); \
status = EHCI_READ_PORT_ULONG( addr ); \
status = ( status & 0xfffffd5 ) & ~( x ); \
EHCI_WRITE_PORT_ULONG( addr, ( ULONG )status ); \
}
#define SET_RH2_PORTSTAT( port_idx, x ) \
{\
PULONG addr; \
addr = ( PULONG )( ehci->port_base + port_idx ); \
status = EHCI_READ_PORT_ULONG( addr ); \
if( x & PORT_PR ) \
status = ( status & 0xffffffd1 ) | ( x ); \
else \
status = ( status & 0xffffffd5 ) | ( x ); \
EHCI_WRITE_PORT_ULONG( addr, ( ULONG )status ); \
}
#define ehci_from_hcd( hCD ) ( struct_ptr( ( hCD ), EHCI_DEV, hcd_interf ) )
#define ehci_from_dev( dEV ) ( ehci_from_hcd( dEV->hcd ) )
#define ehci_copy_overlay( pQHC, pTDC ) \
{\
LONG td_size;\
PEHCI_QH pqh1;\
PEHCI_QTD ptd1;\
pqh1 = ( PEHCI_QH )( pQHC );\
ptd1 = ( PEHCI_QTD )( pTDC );\
td_size = get_elem_phys_part_size( INIT_LIST_FLAG_QTD );\
( pQHC )->cur_qtd_ptr = ptd1->phys_addr;\
RtlZeroMemory( &( pQHC )->cur_qtd, td_size );\
( pQHC )->cur_qtd.data_toggle = ( pTDC )->data_toggle;\
pqh1->hw_qtd_next = ptd1->phys_addr;\
pqh1->hw_alt_next = EHCI_PTR_TERM;\
}
//declarations
typedef struct
{
union
{
PUHCI_DEV uhci;
PEHCI_DEV ehci;
};
PVOID context;
ULONG ret;
} SYNC_PARAM, *PSYNC_PARAM;
PDEVICE_OBJECT
ehci_alloc(PDRIVER_OBJECT drvr_obj, PUNICODE_STRING reg_path, ULONG bus_addr, PUSB_DEV_MANAGER dev_mgr);
BOOLEAN ehci_init_schedule(PEHCI_DEV ehci, PADAPTER_OBJECT padapter);
BOOLEAN ehci_release(PDEVICE_OBJECT pdev);
static VOID ehci_stop(PEHCI_DEV ehci);
BOOLEAN ehci_destroy_schedule(PEHCI_DEV ehci);
BOOLEAN NTAPI ehci_sync_insert_urb_schedule(PVOID context);
VOID ehci_init_hcd_interface(PEHCI_DEV ehci);
NTSTATUS ehci_rh_submit_urb(PUSB_DEV rh, PURB purb);
NTSTATUS ehci_dispatch_irp(IN PDEVICE_OBJECT DeviceObject, IN PIRP irp);
VOID ehci_generic_urb_completion(PURB purb, PVOID context);
static NTSTATUS ehci_internal_submit_bulk(PEHCI_DEV ehci, PURB purb);
static NTSTATUS ehci_internal_submit_int(PEHCI_DEV ehci, PURB purb);
static NTSTATUS ehci_internal_submit_ctrl(PEHCI_DEV ehci, PURB purb);
static NTSTATUS ehci_internal_submit_iso(PEHCI_DEV ehci, PURB purb);
static ULONG ehci_scan_iso_error(PEHCI_DEV ehci, PURB purb);
BOOLEAN ehci_claim_bandwidth(PEHCI_DEV ehci, PURB purb, BOOLEAN claim_bw); //true to claim band-width, false to free band-width
static VOID ehci_insert_bulk_schedule(PEHCI_DEV ehci, PURB purb);
#define ehci_insert_control_schedule ehci_insert_bulk_schedule
static VOID ehci_insert_int_schedule(PEHCI_DEV ehci, PURB purb);
static VOID ehci_insert_iso_schedule(PEHCI_DEV ehci, PURB purb);
#define ehci_remove_control_from_schedule ehci_remove_bulk_from_schedule
PDEVICE_OBJECT ehci_probe(PDRIVER_OBJECT drvr_obj, PUNICODE_STRING reg_path, PUSB_DEV_MANAGER dev_mgr);
PDEVICE_OBJECT ehci_create_device(PDRIVER_OBJECT drvr_obj, PUSB_DEV_MANAGER dev_mgr);
BOOLEAN ehci_delete_device(PDEVICE_OBJECT pdev);
VOID ehci_get_capabilities(PEHCI_DEV ehci, PBYTE base);
BOOLEAN NTAPI ehci_isr(PKINTERRUPT interrupt, PVOID context);
BOOLEAN ehci_start(PHCD hcd);
extern VOID rh_timer_svc_reset_port_completion(PUSB_DEV dev, PVOID context);
extern VOID rh_timer_svc_int_completion(PUSB_DEV dev, PVOID context);
extern USB_DEV_MANAGER g_dev_mgr;
#ifndef INCLUDE_EHCI
ULONG debug_level = DBGLVL_MAXIMUM;
PDRIVER_OBJECT usb_driver_obj = NULL;
//pending endpoint pool funcs
VOID
ehci_wait_ms(PEHCI_DEV ehci, LONG ms)
{
LARGE_INTEGER lms;
if (ms <= 0)
return;
lms.QuadPart = -10 * ms;
KeSetTimer(&ehci->reset_timer, lms, NULL);
KeWaitForSingleObject(&ehci->reset_timer, Executive, KernelMode, FALSE, NULL);
return;
}
BOOLEAN
init_pending_endp_pool(PUHCI_PENDING_ENDP_POOL pool)
{
int i;
if (pool == NULL)
return FALSE;
pool->pending_endp_array =
usb_alloc_mem(NonPagedPool, sizeof(UHCI_PENDING_ENDP) * UHCI_MAX_PENDING_ENDPS);
InitializeListHead(&pool->free_que);
pool->free_count = 0;
pool->total_count = UHCI_MAX_PENDING_ENDPS;
KeInitializeSpinLock(&pool->pool_lock);
for(i = 0; i < MAX_TIMER_SVCS; i++)
{
free_pending_endp(pool, &pool->pending_endp_array[i]);
}
return TRUE;
}
BOOLEAN
free_pending_endp(PUHCI_PENDING_ENDP_POOL pool, PUHCI_PENDING_ENDP pending_endp)
{
if (pool == NULL || pending_endp == NULL)
{
return FALSE;
}
RtlZeroMemory(pending_endp, sizeof(UHCI_PENDING_ENDP));
InsertTailList(&pool->free_que, (PLIST_ENTRY) & pending_endp->endp_link);
pool->free_count++;
return TRUE;
}
PUHCI_PENDING_ENDP
alloc_pending_endp(PUHCI_PENDING_ENDP_POOL pool, LONG count)
{
PUHCI_PENDING_ENDP new;
if (pool == NULL || count != 1)
return NULL;
if (pool->free_count <= 0)
return NULL;
new = (PUHCI_PENDING_ENDP) RemoveHeadList(&pool->free_que);
pool->free_count--;
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