?? adsmx21_defs.h
字號:
/*------------------------------------------------------------------------------
[BASIC]
{
[FILENAME] Adsmx21.h
[CONTENT] Hardware register definition for MC9328MX21
[AUTHOR] wangyf
[VERSION] 2006.07.20
[COMPANY] APLUS COMMUNICATION TECHNOLOGY (BeiJing) CO.,LTD
}
[MOD]
{
2006.07.20:
1.Create initial version
}
------------------------------------------------------------------------------*/
#ifndef _ADSMX21_DEFS_H_
#define _ADSMX21_DEFS_H_
#ifndef TRUE
#define TRUE 1
#define FALSE 0
#endif
#define MAPIO (*(volatile unsigned short *)0xcc800000)
/*-----------------------------------------------------------------------------
PLL Module
------------------------------------------------------------------------------*/
#define CSCR (*(volatile unsigned *)0x10027000) /* Clock Source Control Register */
#define MPCTL0 (*(volatile unsigned *)0x10027004) /* MPLL Control Register 0 */
#define MPCTL1 (*(volatile unsigned *)0x10027008) /* MPLL Control Register 1 */
#define SPCTL0 (*(volatile unsigned *)0x1002700c) /* SPLL Control Register 0 */
#define SPCTL1 (*(volatile unsigned *)0x10027010) /* SPLL Control Register 1 */
#define OSC26MCTL (*(volatile unsigned *)0x10027014) /* Oscillator 26M Register */
#define PCDR0 (*(volatile unsigned *)0x10027018) /* Peripheral Clock Divider Register 0 */
#define PCDR1 (*(volatile unsigned *)0x1002701c) /* Peripheral Clock Divider Register 1 */
#define PCCR0 (*(volatile unsigned *)0x10027020) /* Peripheral Clock Control Register 0 */
#define PCCR1 (*(volatile unsigned *)0x10027024) /* Peripheral Clock Control Register 1 */
#define CCSR (*(volatile unsigned *)0x10027028) /* Clock Control Status Register */
#define PMCTL (*(volatile unsigned *)0x1002702c) /* PMOS Switch Control Register */
#define PMCOUNT (*(volatile unsigned *)0x10027030) /* PMOS Switch Counter Register */
#define WKGDCTL (*(volatile unsigned *)0x10027034) /* Wakeup Guard Mode Control Register */
/*-----------------------------------------------------------------------------
AITC (interrupt)Control Module
------------------------------------------------------------------------------*/
#define INTCNTL (*(volatile unsigned *)0x10040000)
#define NIMASK (*(volatile unsigned *)0x10040004)
#define INTENNUM (*(volatile unsigned *)0x10040008)
#define INTDISNUM (*(volatile unsigned *)0x1004000c)
#define INTENABLEH (*(volatile unsigned *)0x10040010)
#define INTENABLEL (*(volatile unsigned *)0x10040014)
#define INTTYPEH (*(volatile unsigned *)0x10040018)
#define INTTYPEL (*(volatile unsigned *)0x1004001c)
#define NIPRIORITY7 (*(volatile unsigned *)0x10040020)
#define NIPRIORITY6 (*(volatile unsigned *)0x10040024)
#define NIPRIORITY5 (*(volatile unsigned *)0x10040028)
#define NIPRIORITY4 (*(volatile unsigned *)0x1004002c)
#define NIPRIORITY3 (*(volatile unsigned *)0x10040030)
#define NIPRIORITY2 (*(volatile unsigned *)0x10040034)
#define NIPRIORITY1 (*(volatile unsigned *)0x10040038)
#define NIPRIORITY0 (*(volatile unsigned *)0x1004003c)
#define NIVECSR (*(volatile unsigned *)0x10040040)
#define FIVECSR (*(volatile unsigned *)0x10040044)
#define INTSRCH (*(volatile unsigned *)0x10040048)
#define INTSRCL (*(volatile unsigned *)0x1004004c)
#define INTFRCH (*(volatile unsigned *)0x10040050)
#define INTFRCL (*(volatile unsigned *)0x10040054)
#define NIPNDH (*(volatile unsigned *)0x10040058)
#define NIPNDL (*(volatile unsigned *)0x1004005c)
#define FIPNDH (*(volatile unsigned *)0x10040060)
#define FIPNDL (*(volatile unsigned *)0x10040064)
#define VECTOR_UDEF0 0 // Vector 0: Unused
#define VECTOR_UDEF1 1 // Vector 1: Unused
#define VECTOR_UDEF2 2 // Vector 2: Unused
#define VECTOR_UDEF3 3 // Vector 3: Unused
#define VECTOR_UDEF4 4 // Vector 4: Unused
#define VECTOR_UDEF5 5 // Vector 5: Unused
#define VECTOR_CSPI3 6 // Vector 6: Configurable SPI(CSPI3)
#define VECTOR_RNGA 7 // Vector 7: Random Number Generator Accelerator(RNGA)
#define VECTOR_GPIO 8 // Vector 8: General Purpose Input/Ouput(GPIO)
#define VECTOR_FIRI 9 // Vector 9: Fast Infra Red Interface(FIRI)
#define VECTOR_SDHC2 10 // Vector 10: Secure Digital Host Controller(SDHC2)
#define VECTOR_SDHC1 11 // Vector 11: Secure Digital Host Controller(SDHC1)
#define VECTOR_I2C 12 // Vector 12: I2C Bus Controller(I2C)
#define VECTOR_SSI2 13 // Vector 13: Synchronous Serial Interface(SSI2)
#define VECTOR_SSI1 14 // Vector 14: Synchronous Serial Interface(SSI1)
#define VECTOR_CSPI2 15 // Vector 15: Configurable SPI(CSPI2)
#define VECTOR_CSPI1 16 // Vector 16: Configurable SPI(CSPI1)
#define VECTOR_UART4 17 // Vector 17: UART4
#define VECTOR_UART3 18 // Vector 18: UART3
#define VECTOR_UART2 19 // Vector 19: UART2
#define VECTOR_UART1 20 // Vector 20: UART1
#define VECTOR_KPP 21 // Vector 21: Key Pad Port(KPP)
#define VECTOR_RTC 22 // Vector 22: Real-Time Clock(RTC)
#define VECTOR_PWM 23 // Vector 23: Pulse Width Modulator(PWM)
#define VECTOR_GPT3 24 // Vector 24: General Purpose Timer(GPT3)
#define VECTOR_GPT2 25 // Vector 25: General Purpose Timer(GPT2)
#define VECTOR_GPT1 26 // Vector 26: General Purpose Timer(GPT1)
#define VECTOR_WDOG 27 // Vector 27: Watchdog(WDOG)
#define VECTOR_PCMCIA 28 // Vector 28: PCMCIA/CF Host Controller(PCMCIA)
#define VECTOR_NFC 29 // Vector 29: Nand Flash Controller(NFC)
#define VECTOR_BMI 30 // Vector 30: Bus Master Interface(BMI)
#define VECTOR_CSI 31 // Vector 31: CMOS Sensor Interface(CSI)
#define VECTOR_DMA0 32 // Vector 32: DMA Channel 0
#define VECTOR_DMA1 33 // Vector 33: DMA Channel 1
#define VECTOR_DMA2 34 // Vector 34: DMA Channel 2
#define VECTOR_DMA3 35 // Vector 35: DMA Channel 3
#define VECTOR_DMA4 36 // Vector 36: DMA Channel 4
#define VECTOR_DMA5 37 // Vector 37: DMA Channel 5
#define VECTOR_DMA6 38 // Vector 38: DMA Channel 6
#define VECTOR_DMA7 39 // Vector 39: DMA Channel 7
#define VECTOR_DMA8 40 // Vector 40: DMA Channel 8
#define VECTOR_DMA9 41 // Vector 41: DMA Channel 9
#define VECTOR_DMA10 42 // Vector 42: DMA Channel 10
#define VECTOR_DMA11 43 // Vector 43: DMA Channel 11
#define VECTOR_DMA12 44 // Vector 44: DMA Channel 12
#define VECTOR_DMA13 45 // Vector 45: DMA Channel 13
#define VECTOR_DMA14 46 // Vector 46: DMA Channel 14
#define VECTOR_DMA15 47 // Vector 47: DMA Channel 15
#define VECTOR_REV48 48 // Vector 48: Reserved
#define VECTOR_eMMA_EN 49 // Vector 49: eMMA Encoder
#define VECTOR_eMMA_DE 50 // Vector 50: eMMA Decoder
#define VECTOR_eMMA_PrP 51 // Vector 51: eMMA Pre Processor
#define VECTOR_eMMA_PP 52 // Vector 52: eMMA Post Processor
#define VECTOR_USB_WAKEUP 53 // Vector 53: USBOTG Wakeup
#define VECTOR_USB_DMA 54 // Vector 54: USBOTG DMA
#define VECTOR_USB_HOST 55 // Vector 55: USBOTG Host
#define VECTOR_USB_FUNC 56 // Vector 56: USBOTG Function
#define VECTOR_USB_HNP 57 // Vector 57: USBOTG HNP
#define VECTOR_USB_CTL 58 // Vector 58: USBOTG Control
#define VECTOR_REV59 59 // Vector 59: Reserved
#define VECTOR_SLCDC 60 // Vector 60: Smart LCD Controller(SLCDC)
#define VECTOR_LCDC 61 // Vector 61: LCD Controller(LCDC)
#define VECTOR_REV62 62 // Vector 62: Reserved
#define VECTOR_REV63 63 // Vector 63: Reserved
/*-----------------------------------------------------------------------------
General Propose Timer Module
------------------------------------------------------------------------------*/
#define TCTL1 (*(volatile unsigned *)0x10003000)
#define TCTL2 (*(volatile unsigned *)0x10004000)
#define TCTL3 (*(volatile unsigned *)0x10005000)
#define TPRER1 (*(volatile unsigned *)0x10003004)
#define TPRER2 (*(volatile unsigned *)0x10004004)
#define TPRER3 (*(volatile unsigned *)0x10005004)
#define TCMP1 (*(volatile unsigned *)0x10003008)
#define TCMP2 (*(volatile unsigned *)0x10004008)
#define TCMP3 (*(volatile unsigned *)0x10005008)
#define TCR1 (*(volatile unsigned *)0x1000300c)
#define TCR2 (*(volatile unsigned *)0x1000400c)
#define TCR3 (*(volatile unsigned *)0x1000500c)
#define TCN1 (*(volatile unsigned *)0x10003010)
#define TCN2 (*(volatile unsigned *)0x10004010)
#define TCN3 (*(volatile unsigned *)0x10005010)
#define TSTAT1 (*(volatile unsigned *)0x10003014)
#define TSTAT2 (*(volatile unsigned *)0x10004014)
#define TSTAT3 (*(volatile unsigned *)0x10005014)
/*-----------------------------------------------------------------------------
SDRAM Memory Control Module
------------------------------------------------------------------------------*/
#define SDCTL0 (*(volatile unsigned *)0xdf000000) /* Sdram 0 Control register */
#define SDCTL1 (*(volatile unsigned *)0xdf000004) /* Sdram 1 Control register */
#define SDRST (*(volatile unsigned *)0xdf000018) /* Sdram Reset register */
#define MISCELLANEOUS (*(volatile unsigned *)0xdf000014) /* Miscellaneous register */
/*-----------------------------------------------------------------------------
External Interface Module
------------------------------------------------------------------------------*/
#define CS0U (*(volatile unsigned *)0xdf001000)
#define CS0L (*(volatile unsigned *)0xdf001004)
#define CS1U (*(volatile unsigned *)0xdf001008)
#define CS1L (*(volatile unsigned *)0xdf00100c)
#define CS2U (*(volatile unsigned *)0xdf001010)
#define CS2L (*(volatile unsigned *)0xdf001014)
#define CS3U (*(volatile unsigned *)0xdf001018)
#define CS3L (*(volatile unsigned *)0xdf00101c)
#define CS4U (*(volatile unsigned *)0xdf001020)
#define CS4L (*(volatile unsigned *)0xdf001024)
#define CS5U (*(volatile unsigned *)0xdf001028)
#define CS5L (*(volatile unsigned *)0xdf00102c)
#define EIM_CNF (*(volatile unsigned *)0xdf001030)
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