/* * linux/include/asm-arm/arch-atmel/hardware.h * for Atmel AT91 series * 2001 Erwin Authried */#ifndef __AT91_INIT_H#define __AT91_INIT_H//chy 2003-01-18#define __arch_putb(v,a)        (*(volatile unsigned char *)(a) = (v))#define __arch_putl(v,a)        (*(volatile unsigned int  *)(a) = (v))#define __arch_getb(a)          (*(volatile unsigned char *)(a))#define __arch_getl(a)          (*(volatile unsigned int  *)(a))#define outb(v,a)  __arch_putb(v,a)#define inb(a)     __arch_getb(a)// chy 2003-01-18#define NETENABLE 1#ifdef NETENABLE#define AT91_NET_BASE    (0xfffa0000)#define AT91_NET_SIZE    255#define AT91_NET_IRQNUM  16   //just IRQ_EXT0#endif/* chy 2002-12-12*/#define HZ 100/* 0=TC0, 1=TC1, 2=TC2 */#define KERNEL_TIMER 1	/* ******************* AT91x40xxx ******************** */#define NR_IRQS		24#define VALID_IRQ(i)	(i<=8 ||(i>=16 && i<NR_IRQS))#define IRQ_FIQ		0#define IRQ_SWI		1#define IRQ_USART0	2#define IRQ_USART1	3#define IRQ_TC0		4#define IRQ_TC1		5#define IRQ_TC2		6#define IRQ_WD		7#define IRQ_PIOA	8#define IRQ_EXT0	16#define IRQ_EXT1	17#define IRQ_EXT2	18#define ARM_CLK		(32768000)#define AT91_USART_CNT 2#define AT91_USART0_BASE	(0xfffd0000)#define AT91_USART1_BASE	(0xfffcc000)#define AT91_TC_BASE		(0xfffe0000)#define AIC_BASE		(0xfffff000)	#define AT91_PIOA_BASE		(0xffff0000)#define AT91_SF_CIDR		(0xfff00000)#define HARD_RESET_NOW()#define HW_AT91_TIMER_INIT(timer)	/* no PMC *//* enable US0,US1 */#define HW_AT91_USART_INIT ((volatile struct pio_regs *)AT91_PIOA_BASE)->pdr = \				PIOA_RXD0|PIOA_TXD0|PIOA_RXD1|PIOA_TXD1; /* PIOA bit allocation */#define PIOA_TCLK0	(1<<0)					#define PIOA_TI0A0	(1<<1)					#define PIOA_TI0B0	(1<<2)					#define PIOA_TCLK1	(1<<3)					#define PIOA_TIOA1	(1<<4)				#define PIOA_TIOB1	(1<<5)				#define PIOA_TCLK2	(1<<6)					#define PIOA_TIOA2	(1<<7)				#define PIOA_TIOB2	(1<<8)				#define PIOA_IRQ0	(1<<9)				#define PIOA_IRQ1	(1<<10)				#define PIOA_IRQ2	(1<<11)				#define PIOA_FIQ	(1<<12)					#define PIOA_SCK0	(1<<13)					#define PIOA_TXD0	(1<<14)					#define PIOA_RXD0	(1<<15)#define PIOA_SCK1	(1<<20)					#define PIOA_TXD1	(1<<21)					#define PIOA_RXD1	(1<<22)#define PIOA_MCK0	(1<<25)	#define PIOA_NCS2	(1<<26)#define PIOA_NCS3	(1<<27)	#define PIOA_A20_CS7	(1<<28)#define PIOA_A21_CS6	(1<<29)	#define PIOA_A22_CS5	(1<<30)#define PIOA_A23_CS4	(1<<31)/* ******************* COMMON PART ******************** */#define AIC_SMR(i)  (AIC_BASE+i*4)#define AIC_IVR	    (AIC_BASE+0x100)#define AIC_FVR	    (AIC_BASE+0x104)#define AIC_ISR	    (AIC_BASE+0x108)#define AIC_IPR	    (AIC_BASE+0x10C)#define AIC_IMR	    (AIC_BASE+0x110)#define AIC_CISR	(AIC_BASE+0x114)#define AIC_IECR	(AIC_BASE+0x120)#define AIC_IDCR	(AIC_BASE+0x124)#define AIC_ICCR	(AIC_BASE+0x128)#define AIC_ISCR	(AIC_BASE+0x12C)#define AIC_EOICR   (AIC_BASE+0x130)#ifndef __ASSEMBLER__struct at91_timer_channel{	unsigned long ccr;				// channel control register		(WO)	unsigned long cmr;				// channel mode register		(RW)	unsigned long reserved[2];			unsigned long cv;				// counter value				(RW)	unsigned long ra;				// register A					(RW)	unsigned long rb;				// register B					(RW)	unsigned long rc;				// register C					(RW)	unsigned long sr;				// status register				(RO)	unsigned long ier;				// interrupt enable register	(WO)	unsigned long idr;				// interrupt disable register	(WO)	unsigned long imr;				// interrupt mask register		(RO)};struct at91_timers{	struct {		struct at91_timer_channel ch;		unsigned char padding[0x40-sizeof(struct at91_timer_channel)];	} chans[3];	unsigned  long bcr;				// block control register		(WO)	unsigned  long bmr;				// block mode	 register		(RW)};#endif/*  TC control register */#define TC_SYNC	(1)/*  TC mode register */#define TC2XC2S(x)	(x & 0x3)#define TC1XC1S(x)	(x<<2 & 0xc)#define TC0XC0S(x)	(x<<4 & 0x30)#define TCNXCNS(timer,v) ((v) << (timer<<1))/* TC channel control */#define TC_CLKEN	(1)			#define TC_CLKDIS	(1<<1)			#define TC_SWTRG	(1<<2)			/* TC interrupts enable/disable/mask and status registers */#define TC_MTIOB	(1<<18)#define TC_MTIOA	(1<<17)#define TC_CLKSTA	(1<<16)#define TC_ETRGS	(1<<7)#define TC_LDRBS	(1<<6)#define TC_LDRAS	(1<<5)#define TC_CPCS		(1<<4)#define TC_CPBS		(1<<3)#define TC_CPAS		(1<<2)#define TC_LOVRS	(1<<1)#define TC_COVFS	(1)/* *	USART registers */#ifndef __ASSEMBLER__struct atmel_usart_regs{	unsigned long cr;		// control 	unsigned long mr;		// mode	unsigned long ier;		// interrupt enable	unsigned long idr;		// interrupt disable	unsigned long imr;		// interrupt mask	unsigned long csr;		// channel status	unsigned long rhr;		// receive holding 	unsigned long thr;		// tramsmit holding			unsigned long brgr;		// baud rate generator			unsigned long rtor;		// rx time-out	unsigned long ttgr;		// tx time-guard	unsigned long res1;	unsigned long rpr;		// rx pointer	unsigned long rcr;		// rx counter	unsigned long tpr;		// tx pointer	unsigned long tcr;		// tx counter};#endif/*  US control register */#define US_SENDA	(1<<12)#define US_STTO		(1<<11)#define US_STPBRK	(1<<10)#define US_STTBRK	(1<<9)#define US_RSTSTA	(1<<8)#define US_TXDIS	(1<<7)#define US_TXEN		(1<<6)#define US_RXDIS	(1<<5)#define US_RXEN		(1<<4)#define US_RSTTX	(1<<3)#define US_RSTRX	(1<<2)/* US mode register */#define US_CLK0		(1<<18)#define US_MODE9	(1<<17)#define US_CHMODE(x)(x<<14 & 0xc000)#define US_NBSTOP(x)(x<<12 & 0x3000)#define US_PAR(x)	(x<<9 & 0xe00)#define US_SYNC		(1<<8)#define US_CHRL(x)	(x<<6 & 0xc0)#define US_USCLKS(x)(x<<4 & 0x30)/* US interrupts enable/disable/mask and status register */#define US_DMSI		(1<<10)#define US_TXEMPTY	(1<<9)#define US_TIMEOUT	(1<<8)#define US_PARE		(1<<7)#define US_FRAME	(1<<6)#define US_OVRE		(1<<5)#define US_ENDTX	(1<<4)#define US_ENDRX	(1<<3)#define US_RXBRK	(1<<2)#define US_TXRDY	(1<<1)#define US_RXRDY	(1)#define US_ALL_INTS (US_DMSI|US_TXEMPTY|US_TIMEOUT|US_PARE|US_FRAME|US_OVRE|US_ENDTX|US_ENDRX|US_RXBRK|US_TXRDY|US_RXRDY)		#define PIO(i)		(1<<i)#ifndef __ASSEMBLER__struct pio_regs{	unsigned long per;	unsigned long pdr;	unsigned long psr;	unsigned long res1;	unsigned long oer;	unsigned long odr;	unsigned long osr;	unsigned long res2;	unsigned long ifer;	unsigned long ifdr;	unsigned long ifsr;	unsigned long res3;	unsigned long sodr;	unsigned long codr;	unsigned long odsr;	unsigned long pdsr;	unsigned long ier;	unsigned long idr;	unsigned long imr;	unsigned long isr;};#endif#ifndef __ASSEMBLER__struct pmc_regs{	unsigned long scer;	unsigned long scdr;	unsigned long scsr;	unsigned long reserved;	unsigned long pcer;	unsigned long pcdr;	unsigned long pcsr;};#endif/* chy 2002-12-12 */#define USR26_MODE	0x00#define FIQ26_MODE	0x01#define IRQ26_MODE	0x02#define SVC26_MODE	0x03#define USR_MODE	0x10#define FIQ_MODE	0x11#define IRQ_MODE	0x12#define SVC_MODE	0x13#define ABT_MODE	0x17#define UND_MODE	0x1b#define SYSTEM_MODE	0x1f#define MODE_MASK	0x1f#define T_BIT		0x20#define F_BIT		0x40#define I_BIT		0x80#define CC_V_BIT	(1 << 28)#define CC_C_BIT	(1 << 29)#define CC_Z_BIT	(1 << 30)#define CC_N_BIT	(1 << 31)#define PCMASK		0#define __sti()		\	({		\	unsigned long temp;				\	__asm__ __volatile__(					\	"mrs	%0, cpsr		@ sti\n"		\	"bic	%0, %0, #128\n"					\	"msr	cpsr_c, %0"					\	: "=r" (temp)						\	:							\	: "memory");						\	})/* * Disable IRQs*/ #define __cli()						\  	({						\	unsigned long temp;				\	__asm__ __volatile__(					\	"mrs	%0, cpsr		@ cli\n"		\	"orr	%0, %0, #128\n"					\	"msr	cpsr_c, %0"					\	: "=r" (temp)						\	:							\	: "memory");						\	})#ifndef __ASSEMBLER__extern void ARMDisableInt(void);extern void ARMEnableInt(void);#endif#if (KERNEL_TIMER==0)#   define KERNEL_TIMER_IRQ_NUM IRQ_TC0#elif (KERNEL_TIMER==1)#   define KERNEL_TIMER_IRQ_NUM IRQ_TC1#elif (KERNEL_TIMER==2)#   define KERNEL_TIMER_IRQ_NUM IRQ_TC2#else#error Wierd -- KERNEL_TIMER is not defined or something....#endif#endif // __AT91_INIT_H