{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_69d.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_69d.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_69d " "Info: Found entity 1: cntr_69d" {  } { { "db/cntr_69d.tdf" "" { Text "D:/Verilog_PS2_1c12/db/cntr_69d.tdf" 25 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_69d lpm_counter0:inst5\|lpm_counter:lpm_counter_component\|cntr_69d:auto_generated " "Info: Elaborating entity \"cntr_69d\" for hierarchy \"lpm_counter0:inst5\|lpm_counter:lpm_counter_component\|cntr_69d:auto_generated\"" {  } { { "lpm_counter.tdf" "auto_generated" { Text "d:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 257 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_scanC data_scanC:inst " "Info: Elaborating entity \"data_scanC\" for hierarchy \"data_scanC:inst\"" {  } { { "PS2.bdf" "inst" { Schematic "D:/Verilog_PS2_1c12/PS2.bdf" { { 40 112 248 168 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 data_scanC.v(46) " "Warning (10230): Verilog HDL assignment warning at data_scanC.v(46): truncated value with size 32 to match size of target (4)" {  } { { "data_scanC.v" "" { Text "D:/Verilog_PS2_1c12/data_scanC.v" 46 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "convert convert:inst1 " "Info: Elaborating entity \"convert\" for hierarchy \"convert:inst1\"" {  } { { "PS2.bdf" "inst1" { Schematic "D:/Verilog_PS2_1c12/PS2.bdf" { { 56 320 472 152 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "shifted convert.v(37) " "Warning (10235): Verilog HDL Always Construct warning at convert.v(37): variable \"shifted\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "convert.v" "" { Text "D:/Verilog_PS2_1c12/convert.v" 37 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "capslocked convert.v(44) " "Warning (10235): Verilog HDL Always Construct warning at convert.v(44): variable \"capslocked\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "convert.v" "" { Text "D:/Verilog_PS2_1c12/convert.v" 44 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "convert.v(59) " "Warning (10270): Verilog HDL statement warning at convert.v(59): incomplete Case Statement has no default case item" {  } { { "convert.v" "" { Text "D:/Verilog_PS2_1c12/convert.v" 59 0 0 } }  } 0 10270 "Verilog HDL statement warning at %1!s!: incomplete Case Statement has no default case item" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "tmpASCII convert.v(53) " "Warning (10240): Verilog HDL Always Construct warning at convert.v(53): variable \"tmpASCII\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"tmpASCII\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "convert.v" "" { Text "D:/Verilog_PS2_1c12/convert.v" 53 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"%1!s!\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mydff convert:inst1\|mydff:dff_component1 " "Info: Elaborating entity \"mydff\" for hierarchy \"convert:inst1\|mydff:dff_component1\"" {  } { { "convert.v" "dff_component1" { Text "D:/Verilog_PS2_1c12/convert.v" 135 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../altera/quartus51/libraries/megafunctions/lpm_ff.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../altera/quartus51/libraries/megafunctions/lpm_ff.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_ff " "Info: Found entity 1: lpm_ff" {  } { { "lpm_ff.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/lpm_ff.tdf" 46 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_ff convert:inst1\|mydff:dff_component1\|lpm_ff:lpm_ff_component " "Info: Elaborating entity \"lpm_ff\" for hierarchy \"convert:inst1\|mydff:dff_component1\|lpm_ff:lpm_ff_component\"" {  } { { "mydff.v" "lpm_ff_component" { Text "D:/Verilog_PS2_1c12/mydff.v" 51 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bin27seg bin27seg:inst3 " "Info: Elaborating entity \"bin27seg\" for hierarchy \"bin27seg:inst3\"" {  } { { "PS2.bdf" "inst3" { Schematic "D:/Verilog_PS2_1c12/PS2.bdf" { { 192 240 424 288 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "convert:inst1\|tmpASCII\[0\] " "Warning: Latch convert:inst1\|tmpASCII\[0\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA data_scanC:inst\|started " "Warning: Ports D and ENA on the latch are fed by the same signal data_scanC:inst\|started" {  } { { "data_scanC.v" "" { Text "D:/Verilog_PS2_1c12/data_scanC.v" 21 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "convert.v" "" { Text "D:/Verilog_PS2_1c12/convert.v" 59 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "convert:inst1\|tmpASCII\[4\] " "Warning: Latch convert:inst1\|tmpASCII\[4\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA data_scanC:inst\|started " "Warning: Ports D and ENA on the latch are fed by the same signal data_scanC:inst\|started" {  } { { "data_scanC.v" "" { Text "D:/Verilog_PS2_1c12/data_scanC.v" 21 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "convert.v" "" { Text "D:/Verilog_PS2_1c12/convert.v" 59 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "convert:inst1\|tmpASCII\[1\] " "Warning: Latch convert:inst1\|tmpASCII\[1\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA data_scanC:inst\|started " "Warning: Ports D and ENA on the latch are fed by the same signal data_scanC:inst\|started" {  } { { "data_scanC.v" "" { Text "D:/Verilog_PS2_1c12/data_scanC.v" 21 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "convert.v" "" { Text "D:/Verilog_PS2_1c12/convert.v" 59 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "convert:inst1\|tmpASCII\[5\] " "Warning: Latch convert:inst1\|tmpASCII\[5\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA data_scanC:inst\|started " "Warning: Ports D and ENA on the latch are fed by the same signal data_scanC:inst\|started" {  } { { "data_scanC.v" "" { Text "D:/Verilog_PS2_1c12/data_scanC.v" 21 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "convert.v" "" { Text "D:/Verilog_PS2_1c12/convert.v" 59 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "convert:inst1\|tmpASCII\[6\] " "Warning: Latch convert:inst1\|tmpASCII\[6\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA data_scanC:inst\|started " "Warning: Ports D and ENA on the latch are fed by the same signal data_scanC:inst\|started" {  } { { "data_scanC.v" "" { Text "D:/Verilog_PS2_1c12/data_scanC.v" 21 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "convert.v" "" { Text "D:/Verilog_PS2_1c12/convert.v" 59 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "convert:inst1\|tmpASCII\[3\] " "Warning: Latch convert:inst1\|tmpASCII\[3\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA data_scanC:inst\|started " "Warning: Ports D and ENA on the latch are fed by the same signal data_scanC:inst\|started" {  } { { "data_scanC.v" "" { Text "D:/Verilog_PS2_1c12/data_scanC.v" 21 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "convert.v" "" { Text "D:/Verilog_PS2_1c12/convert.v" 59 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "convert:inst1\|tmpASCII\[2\] " "Warning: Latch convert:inst1\|tmpASCII\[2\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA data_scanC:inst\|started " "Warning: Ports D and ENA on the latch are fed by the same signal data_scanC:inst\|started" {  } { { "data_scanC.v" "" { Text "D:/Verilog_PS2_1c12/data_scanC.v" 21 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "convert.v" "" { Text "D:/Verilog_PS2_1c12/convert.v" 59 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "245 " "Info: Implemented 245 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "4 " "Info: Implemented 4 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "11 " "Info: Implemented 11 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "230 " "Info: Implemented 230 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 29 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 29 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Nov 19 23:02:46 2006 " "Info: Processing ended: Sun Nov 19 23:02:46 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:29 " "Info: Elapsed time: 00:00:29" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}