V3 30
FL $XILINX/verilog/src/glbl.v 2006/12/01.18:44:50 J.30
FL D:/PY/Widecom/i2c_2_x/i2c/../i2ctb.v 2007/11/20.02:22:19 J.30
FL D:/PY/Widecom/i2c_2_x/i2c/netgen/fit/i2c_timesim.v 2007/11/20.02:16:50 J.30
FL D:/PY/Widecom/i2c_x/i2c/../i2ctb.v 2008/01/02.15:31:09 J.30
MO work/i2ctb_v FL D:/PY/Widecom/i2c_x/i2c/../i2ctb.v MI i2c
FL D:/PY/Widecom/i2c_x/i2c/netgen/fit/i2c_timesim.v 2008/01/02.15:32:38 J.30
MO work/i2c FL D:/PY/Widecom/i2c_x/i2c/netgen/fit/i2c_timesim.v MI X_AND16 \
      MI X_AND2 MI X_AND3 MI X_AND4 MI X_AND5 MI X_AND6 MI X_AND7 MI X_BUF MI X_FF \
      MI X_INV MI X_IPAD MI X_ONE MI X_OPAD MI X_OR2 MI X_OR3 MI X_OR32 MI X_OR5 \
      MI X_OR6 MI X_TRI MI X_XOR2 MI X_ZERO
MO work/glbl \
      FL D:/PY/Widecom/i2c_x/i2c/netgen/fit/i2c_timesim.v