MO top_uart NULL F:/RHicdemo/sp3s_demo/pro104/rtl/verilog/top_uart.v vlg32/top__uart.bin 1162601577
MO uart_char_rom NULL F:/RHicdemo/sp3s_demo/pro104/rtl/verilog/uart_char_rom.v vlg7A/uart__char__rom.bin 1162601577
MO sp3s_top NULL F:/RHicdemo/sp3s_demo/pro104/rtl/verilog/sp3s_top.v vlg4B/sp3s__top.bin 1162601412
MO uart_clk_50m NULL F:/RHicdemo/sp3s_demo/pro104/rtl/verilog/uart_clk_50m.v vlg7A/uart__clk__50m.bin 1162601577
MO uart_rx NULL F:/RHicdemo/sp3s_demo/pro104/rtl/verilog/uart_rx.v vlg21/uart__rx.bin 1162601577
MO uart_tx NULL F:/RHicdemo/sp3s_demo/pro104/rtl/verilog/uart_tx.v vlg2B/uart__tx.bin 1162601577