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Release 8.1.03i Trace I.27
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

D:\Xilinx\bin\nt\trce.exe -ise ise81_verilog.ise -intstyle ise -e 3 -l 3 -s 4
-xml top_uart top_uart.ncd -o top_uart.twr top_uart.pcf


Design file:              top_uart.ncd
Physical constraint file: top_uart.pcf
Device,speed:             xc3s200,-4 (PRODUCTION 1.37 2005-11-04)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    4.917|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Sat Nov 04 08:53:50 2006
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Peak Memory Usage: 104 MB