Release 8.1.03i - xst I.27Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.--> Parameter TMPDIR set to ./xst/projnav.tmpCPU : 0.00 / 0.47 s | Elapsed : 0.00 / 1.00 s --> Parameter xsthdpdir set to ./xstCPU : 0.00 / 0.47 s | Elapsed : 0.00 / 1.00 s --> Reading design: top_uart.prjTABLE OF CONTENTS  1) Synthesis Options Summary  2) HDL Compilation  3) HDL Analysis  4) HDL Synthesis     4.1) HDL Synthesis Report  5) Advanced HDL Synthesis     5.1) Advanced HDL Synthesis Report  6) Low Level Synthesis  7) Final Report     7.1) Device utilization summary     7.2) TIMING REPORT=========================================================================*                      Synthesis Options Summary                        *=========================================================================---- Source ParametersInput File Name                    : "top_uart.prj"Input Format                       : mixedIgnore Synthesis Constraint File   : NO---- Target ParametersOutput File Name                   : "top_uart"Output Format                      : NGCTarget Device                      : xc3s200-4-pq208---- Source OptionsTop Module Name                    : top_uartAutomatic FSM Extraction           : YESFSM Encoding Algorithm             : AutoFSM Style                          : lutRAM Extraction                     : YesRAM Style                          : AutoROM Extraction                     : YesMux Style                          : AutoDecoder Extraction                 : YESPriority Encoder Extraction        : YESShift Register Extraction          : YESLogical Shifter Extraction         : YESXOR Collapsing                     : YESROM Style                          : AutoMux Extraction                     : YESResource Sharing                   : YESMultiplier Style                   : autoAutomatic Register Balancing       : No---- Target OptionsAdd IO Buffers                     : YESGlobal Maximum Fanout              : 500Add Generic Clock Buffer(BUFG)     : 8Register Duplication               : YESSlice Packing                      : YESPack IO Registers into IOBs        : autoEquivalent register Removal        : YES---- General OptionsOptimization Goal                  : SpeedOptimization Effort                : 1Keep Hierarchy                     : NORTL Output                         : YesGlobal Optimization                : AllClockNetsWrite Timing Constraints           : NOHierarchy Separator                : /Bus Delimiter                      : <>Case Specifier                     : maintainSlice Utilization Ratio            : 100Slice Utilization Ratio Delta      : 5---- Other Optionslso                                : top_uart.lsoRead Cores                         : YEScross_clock_analysis               : NOverilog2001                        : YESsafe_implementation                : NoOptimize Instantiated Primitives   : NOuse_clock_enable                   : Yesuse_sync_set                       : Yesuse_sync_reset                     : Yes==================================================================================================================================================*                          HDL Compilation                              *=========================================================================Compiling verilog file "F:/RHicdemo/sp3s_demo/pro104/rtl/verilog/uart_tx.v" in library workCompiling verilog file "F:/RHicdemo/sp3s_demo/pro104/rtl/verilog/uart_rx.v" in library workModule <uart_tx> compiledCompiling verilog file "F:/RHicdemo/sp3s_demo/pro104/rtl/verilog/uart_clk_50m.v" in library workModule <uart_rx> compiledCompiling verilog file "F:/RHicdemo/sp3s_demo/pro104/rtl/verilog/uart_char_rom.v" in library workModule <uart_clk_50m> compiledCompiling verilog file "F:/RHicdemo/sp3s_demo/pro104/rtl/verilog/top_uart.v" in library workModule <uart_char_rom> compiledModule <top_uart> compiledNo errors in compilationAnalysis of file <"top_uart.prj"> succeeded. =========================================================================*                            HDL Analysis                               *=========================================================================Analyzing top module <top_uart>.Module <top_uart> is correct for synthesis.     Set property "clock_buffer = ibufg" for signal <rst_n> in unit <top_uart>.Analyzing module <uart_clk_50m>.Module <uart_clk_50m> is correct for synthesis. Analyzing module <uart_rx>.Module <uart_rx> is correct for synthesis. Analyzing module <uart_tx>.Module <uart_tx> is correct for synthesis. Analyzing module <uart_char_rom>.Module <uart_char_rom> is correct for synthesis. =========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <uart_char_rom>.    Related source file is "F:/RHicdemo/sp3s_demo/pro104/rtl/verilog/uart_char_rom.v".    Found 512x8-bit ROM for signal <data>.    Summary:	inferred   1 ROM(s).Unit <uart_char_rom> synthesized.Synthesizing Unit <uart_tx>.    Related source file is "F:/RHicdemo/sp3s_demo/pro104/rtl/verilog/uart_tx.v".    Found 1-bit register for signal <tbre>.    Found 1-bit register for signal <txd>.    Found 1-bit register for signal <tsre>.    Found 1-bit register for signal <sdo>.    Found 1-bit 4-to-1 multiplexer for signal <$n0005>.    Found 1-bit 4-to-1 multiplexer for signal <$n0006>.    Found 1-bit 4-to-1 multiplexer for signal <$n0007>.    Found 1-bit 4-to-1 multiplexer for signal <$n0008>.    Found 1-bit 4-to-1 multiplexer for signal <$n0009>.    Found 1-bit 4-to-1 multiplexer for signal <$n0010>.    Found 1-bit 4-to-1 multiplexer for signal <$n0011>.    Found 1-bit 4-to-1 multiplexer for signal <$n0012>.    Found 1-bit 4-to-1 multiplexer for signal <$n0013>.    Found 4-bit 4-to-1 multiplexer for signal <$n0014>.    Found 8-bit 4-to-1 multiplexer for signal <$n0016>.    Found 1-bit 4-to-1 multiplexer for signal <$n0017>.    Found 4-bit adder for signal <$n0018> created at line 199.    Found 1-bit 4-to-1 multiplexer for signal <$n0022>.    Found 1-bit xor2 for signal <$n0023> created at line 134.    Found 1-bit 4-to-1 multiplexer for signal <$n0024>.    Found 1-bit 4-to-1 multiplexer for signal <$n0025>.    Found 1-bit 4-to-1 multiplexer for signal <$n0026>.    Found 1-bit 4-to-1 multiplexer for signal <$n0027>.    Found 1-bit 4-to-1 multiplexer for signal <$n0028>.    Found 1-bit 4-to-1 multiplexer for signal <$n0029>.    Found 1-bit 4-to-1 multiplexer for signal <$n0030>.    Found 1-bit 4-to-1 multiplexer for signal <$n0031>.    Found 8-bit 4-to-1 multiplexer for signal <$n0035>.    Found 1-bit 4-to-1 multiplexer for signal <$n0037>.    Found 1-bit xor2 for signal <$n0038> created at line 221.    Found 4-bit comparator greatequal for signal <$n0067> created at line 129.    Found 4-bit comparator lessequal for signal <$n0068> created at line 129.    Found 4-bit comparator greatequal for signal <$n0076> created at line 218.    Found 4-bit comparator lessequal for signal <$n0077> created at line 218.    Found 1-bit register for signal <clk1x_enable>.    Found 4-bit up counter for signal <clkdiv>.    Found 8-bit register for signal <din_latch1>.    Found 8-bit register for signal <din_latch2>.    Found 4-bit up counter for signal <no_bits_sent>.    Found 1-bit register for signal <parity>.    Found 1-bit register for signal <parity_bit>.    Found 4-bit register for signal <sent_bit>.    Found 8-bit register for signal <tbr>.    Found 8-bit register for signal <tsr>.    Found 4-bit up counter for signal <tx_clk_cnt>.    Found 1-bit register for signal <wr_n_z>.    Found 1-bit register for signal <wr_n_zz>.    Found 1-bit register for signal <wrn1>.    Found 1-bit register for signal <wrn2>.    Summary:	inferred   3 Counter(s).	inferred  47 D-type flip-flop(s).	inferred   1 Adder/Subtractor(s).	inferred   4 Comparator(s).	inferred  40 Multiplexer(s).Unit <uart_tx> synthesized.Synthesizing Unit <uart_rx>.    Related source file is "F:/RHicdemo/sp3s_demo/pro104/rtl/verilog/uart_rx.v".    Found 1-bit register for signal <parity_error>.    Found 1-bit register for signal <data_ready>.    Found 1-bit register for signal <framing_error>.    Found 1-bit xor2 for signal <$n0008> created at line 114.    Found 4-bit comparator greatequal for signal <$n0014> created at line 110.    Found 4-bit comparator lessequal for signal <$n0015> created at line 110.    Found 1-bit register for signal <clk1x_enable>.    Found 4-bit up counter for signal <clkdiv>.    Found 4-bit up counter for signal <no_bits_rcvd>.    Found 1-bit register for signal <parity>.    Found 8-bit register for signal <rbr>.    Found 8-bit register for signal <rsr>.    Found 1-bit register for signal <rxd1>.    Found 1-bit register for signal <rxd2>.    Summary:	inferred   2 Counter(s).	inferred  23 D-type flip-flop(s).	inferred   2 Comparator(s).Unit <uart_rx> synthesized.Synthesizing Unit <uart_clk_50m>.