-- Description : final add block for CLA (1 bit add)
library IEEE;
library work;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.STD_LOGIC_ARITH.ALL;
 use IEEE.STD_LOGIC_UNSIGNED.ALL;
 use work.all;

 entity add is port (
 c : in std_logic;
 t : in std_logic;
 g : in std_logic;
 z : out std_logic);
 end add;
 architecture behavioral of add is
 begin
 z <= (not g and t) xor c ;
 end behavioral;