?? at91sam9263.h
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// ----------------------------------------------------------------------------
// ATMEL Microcontroller Software Support - ROUSSET -
// ----------------------------------------------------------------------------
// Copyright (c) 2006, Atmel Corporation
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the disclaimer below.
//
// Atmel's name may not be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ----------------------------------------------------------------------------
// File Name : AT91SAM9263.h
// Object : AT91SAM9263 definitions
// Generated : AT91 SW Application Group 09/10/2008 (16:04:09)
//
// CVS Reference : /AT91SAM9263.pl/1.2/Fri Nov 10 12:53:28 2006//
// CVS Reference : /SYS_SAM9262.pl/1.4/Tue Jan 18 17:06:33 2005//
// CVS Reference : /HMATRIX1_SAM9262.pl/1.10/Thu Oct 13 12:44:26 2005//
// CVS Reference : /CCR_SAM9262.pl/1.7/Mon Nov 13 08:41:51 2006//
// CVS Reference : /PMC_SAM9262.pl/1.4/Mon Mar 7 18:03:13 2005//
// CVS Reference : /HSDRAMC1_6100A.pl/1.2/Mon Aug 9 10:52:25 2004//
// CVS Reference : /HSMC3_6105A.pl/1.5/Thu Jun 5 15:27:27 2008//
// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005//
// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005//
// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005//
// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005//
// CVS Reference : /RSTC_6098A.pl/1.3/Thu Nov 4 13:57:00 2004//
// CVS Reference : /SHDWC_6122A.pl/1.3/Wed Oct 6 14:16:58 2004//
// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004//
// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004//
// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004//
// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005//
// CVS Reference : /MCI_6101E.pl/1.1/Fri Jun 3 13:20:23 2005//
// CVS Reference : /TWI_6061A.pl/1.2/Fri Oct 27 11:40:48 2006//
// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005//
// CVS Reference : /SSC_6078B.pl/1.2/Wed Apr 16 08:28:18 2008//
// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005//
// CVS Reference : /AC97C_XXXX.pl/1.3/Tue Feb 22 17:08:27 2005//
// CVS Reference : /CAN_6019B.pl/1.1/Mon Jan 31 13:54:30 2005//
// CVS Reference : /PWM_6044D.pl/1.2/Tue May 10 12:39:09 2005//
// CVS Reference : /LCDC_6063A.pl/1.5/Mon Jun 30 09:38:02 2008//
// CVS Reference : /EMACB_6119A.pl/1.6/Wed Jul 13 15:25:00 2005//
// CVS Reference : /DMA_XXXX.pl/1.6/Tue Jan 11 09:40:44 2005//
// CVS Reference : /UDP_6ept_puon.pl/1.1/Thu Aug 3 12:46:31 2006//
// CVS Reference : /UHP_6127A.pl/1.1/Wed Feb 23 16:03:17 2005//
// CVS Reference : /TBOX_XXXX.pl/1.15/Thu Jun 9 07:05:57 2005//
// CVS Reference : /EBI_nadia2.pl/1.1/Wed Dec 29 11:28:03 2004//
// CVS Reference : /HECC_6143A.pl/1.1/Wed Feb 9 17:16:57 2005//
// CVS Reference : /ISI_xxxxx.pl/1.6/Mon Sep 1 14:41:33 2008//
// ----------------------------------------------------------------------------
#ifndef AT91SAM9263_H
#define AT91SAM9263_H
#ifndef __ASSEMBLY__
typedef volatile unsigned int AT91_REG;// Hardware register definition
#define AT91_CAST(a) (a)
#else
#define AT91_CAST(a)
#endif
// *****************************************************************************
// SOFTWARE API DEFINITION FOR System Peripherals
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_SYS {
AT91_REG SYS_ECC0; // ECC 0
AT91_REG Reserved0[127]; //
AT91_REG SYS_SDRAMC0_MR; // SDRAM Controller Mode Register
AT91_REG SYS_SDRAMC0_TR; // SDRAM Controller Refresh Timer Register
AT91_REG SYS_SDRAMC0_CR; // SDRAM Controller Configuration Register
AT91_REG SYS_SDRAMC0_HSR; // SDRAM Controller High Speed Register
AT91_REG SYS_SDRAMC0_LPR; // SDRAM Controller Low Power Register
AT91_REG SYS_SDRAMC0_IER; // SDRAM Controller Interrupt Enable Register
AT91_REG SYS_SDRAMC0_IDR; // SDRAM Controller Interrupt Disable Register
AT91_REG SYS_SDRAMC0_IMR; // SDRAM Controller Interrupt Mask Register
AT91_REG SYS_SDRAMC0_ISR; // SDRAM Controller Interrupt Mask Register
AT91_REG SYS_SDRAMC0_MDR; // SDRAM Memory Device Register
AT91_REG Reserved1[118]; //
AT91_REG SYS_SMC0_SETUP0; // Setup Register for CS 0
AT91_REG SYS_SMC0_PULSE0; // Pulse Register for CS 0
AT91_REG SYS_SMC0_CYCLE0; // Cycle Register for CS 0
AT91_REG SYS_SMC0_CTRL0; // Control Register for CS 0
AT91_REG SYS_SMC0_SETUP1; // Setup Register for CS 1
AT91_REG SYS_SMC0_PULSE1; // Pulse Register for CS 1
AT91_REG SYS_SMC0_CYCLE1; // Cycle Register for CS 1
AT91_REG SYS_SMC0_CTRL1; // Control Register for CS 1
AT91_REG SYS_SMC0_SETUP2; // Setup Register for CS 2
AT91_REG SYS_SMC0_PULSE2; // Pulse Register for CS 2
AT91_REG SYS_SMC0_CYCLE2; // Cycle Register for CS 2
AT91_REG SYS_SMC0_CTRL2; // Control Register for CS 2
AT91_REG SYS_SMC0_SETUP3; // Setup Register for CS 3
AT91_REG SYS_SMC0_PULSE3; // Pulse Register for CS 3
AT91_REG SYS_SMC0_CYCLE3; // Cycle Register for CS 3
AT91_REG SYS_SMC0_CTRL3; // Control Register for CS 3
AT91_REG SYS_SMC0_SETUP4; // Setup Register for CS 4
AT91_REG SYS_SMC0_PULSE4; // Pulse Register for CS 4
AT91_REG SYS_SMC0_CYCLE4; // Cycle Register for CS 4
AT91_REG SYS_SMC0_CTRL4; // Control Register for CS 4
AT91_REG SYS_SMC0_SETUP5; // Setup Register for CS 5
AT91_REG SYS_SMC0_PULSE5; // Pulse Register for CS 5
AT91_REG SYS_SMC0_CYCLE5; // Cycle Register for CS 5
AT91_REG SYS_SMC0_CTRL5; // Control Register for CS 5
AT91_REG SYS_SMC0_SETUP6; // Setup Register for CS 6
AT91_REG SYS_SMC0_PULSE6; // Pulse Register for CS 6
AT91_REG SYS_SMC0_CYCLE6; // Cycle Register for CS 6
AT91_REG SYS_SMC0_CTRL6; // Control Register for CS 6
AT91_REG SYS_SMC0_SETUP7; // Setup Register for CS 7
AT91_REG SYS_SMC0_PULSE7; // Pulse Register for CS 7
AT91_REG SYS_SMC0_CYCLE7; // Cycle Register for CS 7
AT91_REG SYS_SMC0_CTRL7; // Control Register for CS 7
AT91_REG Reserved2[96]; //
AT91_REG SYS_ECC1; // ECC 0
AT91_REG Reserved3[127]; //
AT91_REG SYS_SDRAMC1_MR; // SDRAM Controller Mode Register
AT91_REG SYS_SDRAMC1_TR; // SDRAM Controller Refresh Timer Register
AT91_REG SYS_SDRAMC1_CR; // SDRAM Controller Configuration Register
AT91_REG SYS_SDRAMC1_HSR; // SDRAM Controller High Speed Register
AT91_REG SYS_SDRAMC1_LPR; // SDRAM Controller Low Power Register
AT91_REG SYS_SDRAMC1_IER; // SDRAM Controller Interrupt Enable Register
AT91_REG SYS_SDRAMC1_IDR; // SDRAM Controller Interrupt Disable Register
AT91_REG SYS_SDRAMC1_IMR; // SDRAM Controller Interrupt Mask Register
AT91_REG SYS_SDRAMC1_ISR; // SDRAM Controller Interrupt Mask Register
AT91_REG SYS_SDRAMC1_MDR; // SDRAM Memory Device Register
AT91_REG Reserved4[118]; //
AT91_REG SYS_SMC1_SETUP0; // Setup Register for CS 0
AT91_REG SYS_SMC1_PULSE0; // Pulse Register for CS 0
AT91_REG SYS_SMC1_CYCLE0; // Cycle Register for CS 0
AT91_REG SYS_SMC1_CTRL0; // Control Register for CS 0
AT91_REG SYS_SMC1_SETUP1; // Setup Register for CS 1
AT91_REG SYS_SMC1_PULSE1; // Pulse Register for CS 1
AT91_REG SYS_SMC1_CYCLE1; // Cycle Register for CS 1
AT91_REG SYS_SMC1_CTRL1; // Control Register for CS 1
AT91_REG SYS_SMC1_SETUP2; // Setup Register for CS 2
AT91_REG SYS_SMC1_PULSE2; // Pulse Register for CS 2
AT91_REG SYS_SMC1_CYCLE2; // Cycle Register for CS 2
AT91_REG SYS_SMC1_CTRL2; // Control Register for CS 2
AT91_REG SYS_SMC1_SETUP3; // Setup Register for CS 3
AT91_REG SYS_SMC1_PULSE3; // Pulse Register for CS 3
AT91_REG SYS_SMC1_CYCLE3; // Cycle Register for CS 3
AT91_REG SYS_SMC1_CTRL3; // Control Register for CS 3
AT91_REG SYS_SMC1_SETUP4; // Setup Register for CS 4
AT91_REG SYS_SMC1_PULSE4; // Pulse Register for CS 4
AT91_REG SYS_SMC1_CYCLE4; // Cycle Register for CS 4
AT91_REG SYS_SMC1_CTRL4; // Control Register for CS 4
AT91_REG SYS_SMC1_SETUP5; // Setup Register for CS 5
AT91_REG SYS_SMC1_PULSE5; // Pulse Register for CS 5
AT91_REG SYS_SMC1_CYCLE5; // Cycle Register for CS 5
AT91_REG SYS_SMC1_CTRL5; // Control Register for CS 5
AT91_REG SYS_SMC1_SETUP6; // Setup Register for CS 6
AT91_REG SYS_SMC1_PULSE6; // Pulse Register for CS 6
AT91_REG SYS_SMC1_CYCLE6; // Cycle Register for CS 6
AT91_REG SYS_SMC1_CTRL6; // Control Register for CS 6
AT91_REG SYS_SMC1_SETUP7; // Setup Register for CS 7
AT91_REG SYS_SMC1_PULSE7; // Pulse Register for CS 7
AT91_REG SYS_SMC1_CYCLE7; // Cycle Register for CS 7
AT91_REG SYS_SMC1_CTRL7; // Control Register for CS 7
AT91_REG Reserved5[96]; //
AT91_REG SYS_MATRIX_MCFG0; // Master Configuration Register 0
AT91_REG SYS_MATRIX_MCFG1; // Master Configuration Register 1
AT91_REG SYS_MATRIX_MCFG2; // Master Configuration Register 2
AT91_REG SYS_MATRIX_MCFG3; // Master Configuration Register 3
AT91_REG SYS_MATRIX_MCFG4; // Master Configuration Register 4
AT91_REG SYS_MATRIX_MCFG5; // Master Configuration Register 5
AT91_REG SYS_MATRIX_MCFG6; // Master Configuration Register 6
AT91_REG SYS_MATRIX_MCFG7; // Master Configuration Register 7
AT91_REG SYS_MATRIX_MCFG8; // Master Configuration Register 8
AT91_REG Reserved6[7]; //
AT91_REG SYS_MATRIX_SCFG0; // Slave Configuration Register 0
AT91_REG SYS_MATRIX_SCFG1; // Slave Configuration Register 1
AT91_REG SYS_MATRIX_SCFG2; // Slave Configuration Register 2
AT91_REG SYS_MATRIX_SCFG3; // Slave Configuration Register 3
AT91_REG SYS_MATRIX_SCFG4; // Slave Configuration Register 4
AT91_REG SYS_MATRIX_SCFG5; // Slave Configuration Register 5
AT91_REG SYS_MATRIX_SCFG6; // Slave Configuration Register 6
AT91_REG SYS_MATRIX_SCFG7; // Slave Configuration Register 7
AT91_REG Reserved7[8]; //
AT91_REG SYS_MATRIX_PRAS0; // PRAS0
AT91_REG SYS_MATRIX_PRBS0; // PRBS0
AT91_REG SYS_MATRIX_PRAS1; // PRAS1
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