// chapter27 SD Interface - gom
#define rSDICON     (*(volatile unsigned *)0x5a000000)	//SDI control
#define rSDIPRE     (*(volatile unsigned *)0x5a000004)	//SDI baud rate prescaler
#define rSDICARG    (*(volatile unsigned *)0x5a000008)	//SDI command argument
#define rSDICCON    (*(volatile unsigned *)0x5a00000c)	//SDI command control
#define rSDICSTA    (*(volatile unsigned *)0x5a000010)	//SDI command status
#define rSDIRSP0    (*(volatile unsigned *)0x5a000014)	//SDI response 0
#define rSDIRSP1    (*(volatile unsigned *)0x5a000018)	//SDI response 1
#define rSDIRSP2    (*(volatile unsigned *)0x5a00001c)	//SDI response 2
#define rSDIRSP3    (*(volatile unsigned *)0x5a000020)	//SDI response 3
#define rSDIDTIMER  (*(volatile unsigned *)0x5a000024)	//SDI data/busy timer
#define rSDIBSIZE   (*(volatile unsigned *)0x5a000028)	//SDI block size
#define rSDIDCON    (*(volatile unsigned *)0x5a00002c)	//SDI data control
#define rSDIDCNT    (*(volatile unsigned *)0x5a000030)	//SDI data remain counter
#define rSDIDSTA    (*(volatile unsigned *)0x5a000034)	//SDI data status
#define rSDIFSTA    (*(volatile unsigned *)0x5a000038)	//SDI FIFO status
#define rSDIIMSK    (*(volatile unsigned *)0x5a00003c)	//SDI interrupt mask. edited for 2442A

#ifdef __BIG_ENDIAN  /* edited for 2442A */
#define rSDIDAT		(*(volatile unsigned *)0x5a00004c)	//SDI data
#define SDIDAT		0x5a00004c  

#else  // Little Endian
#define rSDIDAT		(*(volatile unsigned *)0x5a000040)	//SDI data 
#define SDIDAT		0x5a000040  
#endif


// chapter28 HS_MMC Interface - gom
#define rHM_SYSAD      	(*(volatile unsigned *)0x4A800000)	//SDI control register
#define rHM_BLKSIZE    	(*(volatile unsigned *)0x4A800004)	//Host buffer boundary and transfer block size register
#define rHM_BLKCNT	    (*(volatile unsigned *)0x4A800006)	//Block count for current transfer
#define rHM_ARGUMENT   	(*(volatile unsigned *)0x4A800008)	//Command Argument
#define rHM_TRNMOD	    (*(volatile unsigned *)0x4A80000C)	//Transfer Mode setting register
#define rHM_CMDREG	    (*(volatile unsigned *)0x4A80000E)	//Command register
#define rHM_RSPREG0    	(*(volatile unsigned *)0x4A800010)	//Response 0
#define rHM_RSPREG1    	(*(volatile unsigned *)0x4A800014)	//Response 1
#define rHM_RSPREG2    	(*(volatile unsigned *)0x4A800018)	//Response 2
#define rHM_RSPREG3    	(*(volatile unsigned *)0x4A80001C)	//Response 3
#define rHM_BDATA      	(*(volatile unsigned *)0x4A800020)	//Buffer Data register
#define rHM_PRNSTS     	(*(volatile unsigned *)0x4A800024)	//Present state
#define rHM_HOSTCTL    	(*(volatile unsigned *)0x4A800028)	//Host control
#define rHM_PWRCON     	(*(volatile unsigned *)0x4A800029)	//Power control
#define rHM_BLKGAP     	(*(volatile unsigned *)0x4A80002A)	//Block Gap control
#define rHM_WAKCON     	(*(volatile unsigned *)0x4A80002B)	//Wakeup control
#define rHM_CLKCON     	(*(volatile unsigned *)0x4A80002C)	//Clock control
#define rHM_TIMEOUTCON  (*(volatile unsigned *)0x4A80002E)	//Time out control
#define rHM_SWRST      	(*(volatile unsigned *)0x4A80002F)	//Software reset
#define rHM_NORINTSTS  	(*(volatile unsigned *)0x4A800030)	//Normal interrupt status
#define rHM_ERRINTSTS  	(*(volatile unsigned *)0x4A800032)	//Error interrupt status
#define rHM_NORINTSTSEN (*(volatile unsigned *)0x4A800034)	//Normal interrupt status enable
#define rHM_ERRINTSTSEN (*(volatile unsigned *)0x4A800036)	//Error interrupt status enable
#define rHM_NORINTSIGEN (*(volatile unsigned *)0x4A800038)	//Normal interrupt signal enable
#define rHM_ERRINTSIGEN (*(volatile unsigned *)0x4A80003A)	//Error interrupt signal enable
#define rHM_ACMD12ERRSTS (*(volatile unsigned *)0x4A80003C)	//Auto CMD12 Error Status
#define rHM_CAPAREG  	(*(volatile unsigned *)0x4A800040)	//Capability
#define rHM_MAXCURR  	(*(volatile unsigned *)0x4A800048)	//Maximum current Capability
#define rHM_CONTROL2  	(*(volatile unsigned *)0x4A800080)	//Control 2
#define rHM_CONTROL3  	(*(volatile unsigned *)0x4A800084)	//Control 3
#define rHM_HCVER  		(*(volatile unsigned *)0x4A8000FE)	//Host controller version


// Exception vector
#define pISR_RESET     	(*(unsigned *)(_ISR_STARTADDRESS+0x0))
#define pISR_UNDEF     	(*(unsigned *)(_ISR_STARTADDRESS+0x4))
#define pISR_SWI       	(*(unsigned *)(_ISR_STARTADDRESS+0x8))
#define pISR_PABORT    	(*(unsigned *)(_ISR_STARTADDRESS+0xc))
#define pISR_DABORT    	(*(unsigned *)(_ISR_STARTADDRESS+0x10))
#define pISR_RESERVED  	(*(unsigned *)(_ISR_STARTADDRESS+0x14))
#define pISR_IRQ       	(*(unsigned *)(_ISR_STARTADDRESS+0x18))
#define pISR_FIQ       	(*(unsigned *)(_ISR_STARTADDRESS+0x1c))


// Interrupt vector
#define pISR_EINT0		(*(unsigned *)(_ISR_STARTADDRESS+0x20))
#define pISR_EINT1		(*(unsigned *)(_ISR_STARTADDRESS+0x24))
#define pISR_EINT2		(*(unsigned *)(_ISR_STARTADDRESS+0x28))
#define pISR_EINT3		(*(unsigned *)(_ISR_STARTADDRESS+0x2c))
#define pISR_EINT4_7	(*(unsigned *)(_ISR_STARTADDRESS+0x30))
#define pISR_EINT8_23	(*(unsigned *)(_ISR_STARTADDRESS+0x34))
#define pISR_CAM		(*(unsigned *)(_ISR_STARTADDRESS+0x38))		
#define pISR_BAT_FLT	(*(unsigned *)(_ISR_STARTADDRESS+0x3c))
#define pISR_TICK		(*(unsigned *)(_ISR_STARTADDRESS+0x40))
#define pISR_WDT_AC97	(*(unsigned *)(_ISR_STARTADDRESS+0x44))   
#define pISR_TIMER0	 	(*(unsigned *)(_ISR_STARTADDRESS+0x48))
#define pISR_TIMER1	 	(*(unsigned *)(_ISR_STARTADDRESS+0x4c))
#define pISR_TIMER2		(*(unsigned *)(_ISR_STARTADDRESS+0x50))
#define pISR_TIMER3		(*(unsigned *)(_ISR_STARTADDRESS+0x54))
#define pISR_TIMER4		(*(unsigned *)(_ISR_STARTADDRESS+0x58))
#define pISR_UART2		(*(unsigned *)(_ISR_STARTADDRESS+0x5c))
#define pISR_LCD		(*(unsigned *)(_ISR_STARTADDRESS+0x60))
#define pISR_DMA		(*(unsigned *)(_ISR_STARTADDRESS+0x64))		//changed at 2443
#define pISR_UART3		(*(unsigned *)(_ISR_STARTADDRESS+0x68))		//changed at 2443
#define pISR_CFCON		(*(unsigned *)(_ISR_STARTADDRESS+0x6c))		//changed at 2443
#define pISR_SDI_1		(*(unsigned *)(_ISR_STARTADDRESS+0x70))		//changed at 2443
#define pISR_SDI_0		(*(unsigned *)(_ISR_STARTADDRESS+0x74))		//changed at 2443
#define pISR_SPI1		(*(unsigned *)(_ISR_STARTADDRESS+0x78))		//changed at 2443
#define pISR_UART1		(*(unsigned *)(_ISR_STARTADDRESS+0x7c))
#define pISR_NFCON		(*(unsigned *)(_ISR_STARTADDRESS+0x80))		
#define pISR_USBD		(*(unsigned *)(_ISR_STARTADDRESS+0x84))
#define pISR_USBH		(*(unsigned *)(_ISR_STARTADDRESS+0x88))
#define pISR_IIC		(*(unsigned *)(_ISR_STARTADDRESS+0x8c))
#define pISR_UART0		(*(unsigned *)(_ISR_STARTADDRESS+0x90))
#define pISR_SPI0		(*(unsigned *)(_ISR_STARTADDRESS+0x94))		//changed at 2443
#define pISR_RTC		(*(unsigned *)(_ISR_STARTADDRESS+0x98))
#define pISR_ADC		(*(unsigned *)(_ISR_STARTADDRESS+0x9c))


// PENDING BIT
#define BIT_EINT0		(0x1)
#define BIT_EINT1		(0x1<<1)
#define BIT_EINT2		(0x1<<2)
#define BIT_EINT3		(0x1<<3)
#define BIT_EINT4_7		(0x1<<4)
#define BIT_EINT8_23	(0x1<<5)
#define BIT_CAM			(0x1<<6)		
#define BIT_BAT_FLT		(0x1<<7)
#define BIT_TICK		(0x1<<8)
#define BIT_WDT_AC97	(0x1<<9)	
#define BIT_TIMER0		(0x1<<10)
#define BIT_TIMER1		(0x1<<11)
#define BIT_TIMER2		(0x1<<12)
#define BIT_TIMER3		(0x1<<13)
#define BIT_TIMER4		(0x1<<14)
#define BIT_UART2		(0x1<<15)
#define BIT_LCD			(0x1<<16)
#define BIT_DMA			(0x1<<17)		//changed at 2443
#define BIT_UART3		(0x1<<18)		//changed at 2443
#define BIT_CFCON		(0x1<<19)		//changed at 2443
#define BIT_SDI1		(0x1<<20)		//changed at 2443
#define BIT_SDI0		(0x1<<21)		//changed at 2443
#define BIT_SPI1		(0x1<<22)		//changed at 2443
#define BIT_UART1		(0x1<<23)
#define BIT_NFCON		(0x1<<24)		
#define BIT_USBD		(0x1<<25)
#define BIT_USBH		(0x1<<26)
#define BIT_IIC			(0x1<<27)
#define BIT_UART0		(0x1<<28)
#define BIT_SPI0		(0x1<<29)		//changed at 2443
#define BIT_RTC			(0x1<<30)
#define BIT_ADC			(0x1<<31)
#define BIT_ALLMSK		(0xffffffff)


// SUB PENDING BIT
#define BIT_SUB_ALLMSK	(0x1fffffff)		//Changed from 0x7fff to 0x1fffffff at 2443
#define BIT_SUB_AC97	(0x1<<28)		//changed at 2443
#define BIT_SUB_WDT		(0x1<<27)		//changed at 2443
#define BIT_SUB_ERR3	(0x1<<26)		//changed at 2443
#define BIT_SUB_TXD3	(0x1<<25)		//changed at 2443
#define BIT_SUB_RXD3	(0x1<<24)		//changed at 2443
#define BIT_SUB_DMA5	(0x1<<23)		//changed at 2443
#define BIT_SUB_DMA4	(0x1<<22)		//changed at 2443
#define BIT_SUB_DMA3	(0x1<<21)		//changed at 2443
#define BIT_SUB_DMA2	(0x1<<20)		//changed at 2443
#define BIT_SUB_DMA1	(0x1<<19)		//changed at 2443
#define BIT_SUB_DMA0	(0x1<<18)		//changed at 2443
#define BIT_SUB_LCD4	(0x1<<17)		//changed at 2443
#define BIT_SUB_LCD3	(0x1<<16)		//changed at 2443
#define BIT_SUB_LCD2	(0x1<<15)		//changed at 2443
#define BIT_SUB_LCD1	(0x1<<14)		//changed at 2443
#define BIT_SUB_CAM_P	(0x1<<12)		
#define BIT_SUB_CAM_C   (0x1<<11)       
#define BIT_SUB_ADC		(0x1<<10)
#define BIT_SUB_TC		(0x1<<9)
#define BIT_SUB_ERR2	(0x1<<8)
#define BIT_SUB_TXD2	(0x1<<7)
#define BIT_SUB_RXD2	(0x1<<6)
#define BIT_SUB_ERR1	(0x1<<5)
#define BIT_SUB_TXD1	(0x1<<4)
#define BIT_SUB_RXD1	(0x1<<3)
#define BIT_SUB_ERR0	(0x1<<2)
#define BIT_SUB_TXD0	(0x1<<1)
#define BIT_SUB_RXD0	(0x1<<0)


#define ClearPending(bit) {\
                rSRCPND = bit;\
                rINTPND = bit;\
                rINTPND;\
                }                                                              
// Wait until rINTPND is changed for the case that the ISR is very short.       
// The effect of reading "rINTPND;" : Waiting until rINTPND is changed.
// When you access any address, write buffer must be cleared if you want to read this address.
// Otherwise, twice interrupt request could be occured per one interrupt.
// in the case that the ISR is very short.

#ifdef __cplusplus
}
#endif

#endif