/* wrSbc405gp.h - Wind River SBC405GP eval board header */

/* Copyright 1984-2001 Wind River Systems, Inc. */

/*
modification history
--------------------
01a,22apr01,gh   created from walnut.h rev 01c
*/

/*
This file contains I/O addresses and related constants for the
wind River SBC405GP BSP.
*/

#ifndef INCwrSbc405gph
#define INCwrSbc405gph

/* generic macros */
#ifndef EIEIO_SYNC
#ifndef __DCC__
#define EIEIO_SYNC  __asm__ volatile ("eieio;sync")
#else
#define EIEIO_SYNC  __asm ("	eieio;sync")
#endif /* __DCC__ */
#endif  /* EIEIO_SYNC */
#ifndef EIEIO
#ifndef __DCC__
#define EIEIO    __asm__ volatile ("eieio")
#else
#define EIEIO    __asm ("	eieio")
#endif /* __DCC__ */
#endif  /* EIEIO */
#ifndef SYNC
#ifndef __DCC__
#define SYNC    __asm__ volatile ("sync")
#else
#define AYNC    __asm ("	sync")
#endif /* __DCC__ */
#endif  /* AYNC */

#define BUS             NONE                 /* no off-board bus interface    */
#define N_SIO_CHANNELS  2                    /* Number of serial I/O channels */

/*
 * Minimum and maximum system clock rates
 */
#define SYS_CLK_RATE_MIN        3            /* minimum system clock rate     */
#define SYS_CLK_RATE_MAX        5000         /* maximum system clock rate     */

/*
 * Walnut clock frequencies
 */
#define ONE_BILLION		(1000 * 1000 * 1000)
#define SYS_CLK_FREQ		33333333		/* 33.333333 MHz from MPC972  */
#define EXT_TIMER_CLK_FREQ	(SYS_CLK_FREQ /* this is not right */)
#define EXT_SER_CLK_FREQ	3686400			/* 3.6864 MHz dedicated clk  */

/* Patch for TMD/usrWdb.c structure problem (SENS) */
#define  FIX_IP_VH

/*
 * Exception Vector Prefix Register value.  Exception vectors will be located
 * at the start of SDRAM.
 */

#define SBC405GP_EVPR_VAL    0x00000000

/*
 * Initial values for UIC interrupt controller polarity, triggering, and
 * critical vs. non-critical.
 */

#define UIC_INTR_POLARITY  0xFFFFFFF0
#define UIC_INTR_TRIGGER   0x00000000
#define UIC_INTR_CRITICAL  0x00000000


/*
 * MMU
 */

#define ONE_K			1024
#define FLASH_SECTOR_SIZE	(128 * ONE_K * 2)

#define FLASH_BASE_ADRS		0xFF000000
#define FLASH_SIZE		    0x01000000

/* The SL811HS is an add-on USB host controller.  
 */

#define SL811H_MEMORY_START  0x70000000
#define SL811H_MEMSIZE	    0x10000000

/*
 * The Ethernet hardware address that is used with EMAC is
 *
 *       0x00A01Ennnnnn
 *
 * where the first three bytes are defined below, and last three bytes are
 * stored in the NVRAM and can be modified by using the function
 * sysLanIbmEmacEnetAddrSet()
 */
/*                            ___ Alignment pad */
/*                           |                  */
/*                          \|/                 */
#define ENET_DEFAULT 0x00A01E00                 /* H.S.I fixed MAC addr */


/*
 * The address of the PHY attached to the MII interface of EMAC.
 */

#define EMAC_PHY_ADRS   1

/*
 * The SBC405GP board has one socket for a 168 pin SDRAM DIMM.
 * The following are offsets in the SDRAM DIMM's presence-detect serial EEPROM.
 * Values at these offsets are are accessed via the 405GP I2C interface, and
 * are used to help configure the SDRAM controller correctly for the
 * properties of the DIMM.
 */
#define SDRAM_NUM_ROWS     3
#define SDRAM_NUM_COLS     4
#define SDRAM_NUM_BANKS    5
#define SDRAM_WIDTH        6
#define SDRAM_NUM_INTBANKS 17
#define SDRAM_MOD_DENSITY  31

/*
 * SBC405GP_ICCR_VAL and SBC405GP_DCCR_VAL define the cachability
 * state of the total effective adress space at a 128 MB granularity
 * for instruction and data.
 * By default memory spaces 0x00000000-0x07ffffff and 0xf8000000-0xfffffffff
 * are set as cached. The rest of the effective adress space is programmed
 * as non-cached.
 * this can be changed here, according to the memory board mapping.
 */

#define SBC405GP_ICCR_VAL            _PPC405_ICCR_DEFAULT_VAL
#define SBC405GP_DCCR_VAL            _PPC405_DCCR_DEFAULT_VAL

#define SBC405GP_PCI_IRQ   28

/*
 * PCI
 */

#define SBC405GP_NUM_PCI_SLOTS   1

#ifdef INCLUDE_PCI
   
/* Translate PCI addresses to virtual addresses (master windows) */

#define PCI_MEMIO2LOCAL(x) (x)
#define LOCAL2PCI_MEMIO(x) (x)

/*
 * Routines for reading or writing PCI I/O or Memory space. These routines are
 * written in assembler and use byte swapping load/store instructions.
 */
#ifndef _ASMLANGUAGE

#undef  PCI_IN_BYTE
#define PCI_IN_BYTE(x)         sysPciInByte (x)
#undef  PCI_IN_WORD
#define PCI_IN_WORD(x)         sysPciInWord (x)
#undef  PCI_IN_LONG
#define PCI_IN_LONG(x)         sysPciInLong (x)
#undef  PCI_OUT_BYTE
#define PCI_OUT_BYTE(x,y)      sysPciOutByte (x,y)
#undef  PCI_OUT_WORD
#define PCI_OUT_WORD(x,y)      sysPciOutWord (x,y)
#undef  PCI_OUT_LONG
#define PCI_OUT_LONG(x,y)      sysPciOutLong (x,y)

#endif /* _ASMLANGUAGE */

/****************************************************************************
 * PCI Autoconfig Configuration Defines - Mandatory stuff that must be defined in
 * order to use vWare's PCI Autoconfig.
 ****************************************************************************/
#define PCI_ADDRESS_REGISTER 0xEEC00000	/* PCI Address Register		 */
#define PCI_DATA_REGISTER	 0xEEC00004	/* PCI Data Register		 */
#define PCI_MEM_ADRS         0x00000000
#define PCI_MEM_SIZE         0x00000000
#define PCI_MEMIO_ADRS	     0x80000000 /* PCI Auto Config Memory Start Address */
#define PCI_MEMIO_SIZE		 0x68000000 /* PCI Auto Config Memory Size		    */
#define PCI_IO_ADRS		     0xE8800000 /* PCI Auto Config IO Start Address	    */
#define PCI_IO_SIZE		     0x06400000 /* PCI Auto Config IO Size	            */
#define PCI_ISA_IO_ADRS	     0xE8000000
#define PCI_ISA_IO_SIZE	     (0x1000)

#define PCICMD            0x04
#define BM_EN             0x0004
#define MEM_EN            0x0002
#define PCI_ASYNC_MODE_EN       0x00001000

#define PCIBASEADDR1      0x14
#define PCIBASEADDR2      0x18
#define PVR_405GP         0x40110000 
#define PVR_405GP_PASS1   0x40110000 
#define PVR_405GP_PASS2   0x40110040 
#define PCIBRDGOPT1       0x4A
#define PCIBRDGOPT2       0x60

#endif /* INCLUDE_PCI */

#ifndef _ASMLANGUAGE

/*
 * System information structure.  It is used to get information about the
 * 405GP PLL and operating frequencies.
 */

typedef struct
    {
    UINT32  pllFwdDiv;
    UINT32  pllFbkDiv;
    UINT32  pllPlbDiv;
    UINT32  pllPciDiv;
    UINT32  pllExtBusDiv;
    UINT32  pllOpbDiv;
    UINT32  freqVCOMhz;             /* in MHz                          */
    UINT32  freqProcessor;
    UINT32  freqPLB;
    UINT32  freqPCI;
    UINT32  pciIntArbEn;            /* Internal PCI arbiter is enabled */
    UINT32  pciClkSync;             /* PCI clock is synchronous        */
    } SYS_INFO;

#endif

#endif  /* INCwrSbc405gph */