/*=============================================================
*	Copyright (c) 2008~2010, CPIT. All Rights Reserved.
*
*	MODULE:  ecpb8548 驅(qū)動(dòng)
*
*	FILENAME: cpb8548Drv.h
*
*	DESCRIPTION:ecpb 8548 驅(qū)動(dòng)程序的宏定義，數(shù)據(jù)結(jié)構(gòu)
*
*
*	HISTORY:
*
*	Date           CR No      Person        Description
*	----------  ------------  ------       -------------
*	2008-05-28                
*
=============================================================*/
#ifndef _CPB8548_DRV_H_
#define  _CPB8548_DRV_H_

#ifdef __cplusplus
extern "C" {
#endif


/*gpio reg define*/#define M85XX_GPIOCR(base)                (CAST(VUINT32 *)((base) + 0xE0030))#define M85XX_GPOUTDR(base)                (CAST(VUINT32 *)((base) + 0xE0040))#define M85XX_GPINDR(base)                (CAST(VUINT32 *)((base) + 0xE0050))
#define M85XX_DEVDISR(base)            (CAST(VUINT32 *)((base) + 0xE0070))



#define TX2OUT BIT6 /*Enables TSEC2_TX[7:0] for use as general-purpose output if the eTSEC2
                                 interface is disabled and eTSEC1 is not configured for 16-bit FIFO mode.*/                           
#define RX2IN BIT7 /*Enables TSEC2_RX[7:0] for use as general-purpose input if the eTSEC2 
                                  interface is disabled and eTSEC1 is not configured for 16-bit FIFO mode.*/
#define PCIOUT BIT14 /*Enables PCI2_AD[15:8] for use as general-purpose output. Note that 
                                   the PCI1 interface must be configured for 32-bit mode AND the PCI2
                                   interface must be disabled.*/                                  
#define PCIIN BIT15 /*Enables PCI2_AD[7:0] for use as general-purpose input. Note that the
                                PCI1 interface must be configured for 32-bit mode AND the PCI2 interface must be disabled.*/                                   
#define GPOUT BIT22 /*Enables GPOUT[24:31] for use as general-purpose output.*/

#define     ETSEC2_DISABLE    BIT25 

#define FPGA_PROG   0x00080000		/* PROG enable low */
#define FPGA_BUSY   0x00100000		/* BUSY high, DONE low */
#define FPGA_CCLK   0x00040000
#define FPGA_DONE   0x00400000
#define FPGA_RDWR   0x00020000
#define FPGA_INIT   0x00200000

#ifdef __cplusplus
}
#endif
#endif/*_ECPB8548_DRV_H_*/