?? psocconfigtbl.lis
字號:
0000 ; Generated by PSoC Designer ver 4.4 b1884 : 14 Jan, 2007
0000 ;
0010 FLAG_XIO_MASK: equ 10h
0008 FLAG_SUPER: equ 08h
0004 FLAG_CARRY: equ 04h
0002 FLAG_ZERO: equ 02h
0001 FLAG_GLOBAL_IE: equ 01h
0000
0000 ;;=============================================================================
0000 ;; Register Space, Bank 0
0000 ;;=============================================================================
0000
0000 ;------------------------------------------------
0000 ; Port Registers
0000 ;------------------------------------------------
0000 ; Port Data Registers
0000 P0DATA: equ 00h ; Port 0 Data Register (RW)
0001 P1DATA: equ 01h ; Port 1 Data Register (RW)
0002 P2DATA: equ 02h ; Port 2 Data Register (RW)
0003 P3DATA: equ 03h ; Port 3 Data Register (RW)
0004 P4DATA: equ 04h ; Port 4 Data Register (RW)
0000 ; PSoC Compatability
0000 PRT0DR: equ 00h ; Port 0 Data Register (RW)(PSoC)
0001 PRT1DR: equ 01h ; Port 1 Data Register (RW)(PSoC)
0002 PRT2DR: equ 02h ; Port 2 Data Register (RW)(PSoC)
0003 PRT3DR: equ 03h ; Port 3 Data Register (RW)(PSoC)
0004 PRT4DR: equ 04h ; Port 4 Data Register (RW)(PSoC)
0000
0000 ; Port/Pin Configuration Registers
0005 P00CR: equ 05h ; P0.0 Configuration Register (RW)
0006 P01CR: equ 06h ; P0.1 Configuration Register (RW)
0007 P02CR: equ 07h ; P0.2 Configuration Register (RW)
0008 P03CR: equ 08h ; P0.3 Configuration Register (RW)
0009 P04CR: equ 09h ; P0.4 Configuration Register (RW)
000A P05CR: equ 0Ah ; P0.5 Configuration Register (RW)
000B P06CR: equ 0Bh ; P0.6 Configuration Register (RW)
000C P07CR: equ 0Ch ; P0.7 Configuration Register (RW)
000D P10CR: equ 0Dh ; P1.0 Configuration Register (RW)
000E P11CR: equ 0Eh ; P1.1 Configuration Register (RW)
000F P12CR: equ 0Fh ; P1.2 Configuration Register (RW)
0010 P13CR: equ 10h ; P1.3 Configuration Register (RW)
0011 P14CR: equ 11h ; P1.4 Configuration Register (RW)
0012 P15CR: equ 12h ; P1.5 Configuration Register (RW)
0013 P16CR: equ 13h ; P1.6 Configuration Register (RW)
0014 P17CR: equ 14h ; P1.7 Configuration Register (RW)
0015 P2CR: equ 15h ; P2.0-P2.7 Configuration Register (RW)
0016 P3CR: equ 16h ; P3.0-P3.7 Configuration Register (RW)
0017 P4CR: equ 17h ; P4.0-P4.7 Configuration Register (RW)
0000
0000 ; Timer Registers
0020 FRTMRL: equ 20h ; Free Running Timer Low (RW)
0021 FRTMRH: equ 21h ; Free Running Timer High (RW)
0022 TCAP0R: equ 22h ; Capture 0 Rising (R)
0023 TCAP1R: equ 23h ; Capture 1 Rising (R)
0024 TCAP0F: equ 24h ; Capture 0 Falling (R)
0025 TCAP1F: equ 25h ; Capture 1 Falling (R)
0026 PITMRL: equ 26h ; Programmable Interval Timer Low (RW)
0027 PITMRH: equ 27h ; Programmable Interval Timer High (RW)
0028 PIRL: equ 28h ; Programmable Interval Timer Reload Low (RW)
0029 PIRH: equ 29h ; Programmable Interval Timer Reload High (RW)
002A TMRCR: equ 2Ah ; Timer Configuration Register (RW)
002B TCAPINTE: equ 2Bh ; Capture Timer Interrupt Enable (RW)
002C TCAPINTS: equ 2Ch ; Capture Timer Interrupt Status (RW)
0000
0000 ; Clock Configuration Registers
0030 CPUCLKCR: equ 30h ; CPU Clock Configuration Register (RW)
0000 CPUCLK_SEL_INT: equ 00h ; CPU Clock Select Internal Oscillator
0001 CPUCLK_SEL_EXT: equ 01h ; CPU Clock Select External Clock
0000 CPUCLK_USBCLK_SEL_INT: equ 00h ; USB Clock Select Internal Clock
0040 CPUCLK_USBCLK_SEL_EXT: equ 40h ; USB Clock Select External Clock
0000 CPUCLK_USBCLK_DIV2_DIS: equ 00h ; USB Clock Divide by 2 disable
0080 CPUCLK_USBCLK_DIV2_ENA: equ 80h ; USB Clock Divide by 2 enable
0000
0031 TMRCLKCR: equ 31h ; Timer Clock Configuration Register (RW)
0000 TMRCLKCR_ITMRCLK_IOSC: equ 00h ; MASK: ITMRCLK Source--Internal Oscillator
0001 TMRCLKCR_ITMRCLK_XOSC: equ 01h ; MASK: ITMRCLK Source--External Oscillator or CLKIN
0002 TMRCLKCR_ITMRCLK_LPO: equ 02h ; MASK: ITMRCLK Source--Low Power Oscillator (32 Khz)
0003 TMRCLKCR_ITMRCLK_TCAPCLK: equ 03h ; MASK: ITMRCLK Source--TCAPCLK
0000 TMRCLKCR_ITMRCLK_DIV_1: equ 00h ; MASK: ITMRCLK Divider Value 1
0004 TMRCLKCR_ITMRCLK_DIV_2: equ 04h ; MASK: ITMRCLK Divider Value 2
0008 TMRCLKCR_ITMRCLK_DIV_3: equ 08h ; MASK: ITMRCLK Divider Value 3
000C TMRCLKCR_ITMRCLK_DIV_4: equ 0Ch ; MASK: ITMRCLK Divider Value 4
0002 TMRCLKCR_ITMRCLK_LPO: equ 02h ; MASK: ITMRCLK Source--Low Power Oscillator (32 Khz)
0000 TMRCLKCR_TCAPCLK_IOSC: equ 00h ; MASK: TCAPCLK Source--Internal Oscillator
0010 TMRCLKCR_TCAPCLK_XOSC: equ 10h ; MASK: TCAPCLK Source--External Oscillator or CLKIN
0020 TMRCLKCR_TCAPCLK_LPO: equ 20h ; MASK: TCAPCLK Source--Low Power Oscillator (32 Khz)
0030 TMRCLKCR_TCAPCLK_DISABLED: equ 30h ; MASK: TCAPCLK Source--DISABLED
0000 TMRCLKCR_TCAPCLK_DIV_2: equ 00h ; MASK: TCAPCLK Divider Value 2
0040 TMRCLKCR_TCAPCLK_DIV_4: equ 40h ; MASK: TCAPCLK Divider Value 4
0080 TMRCLKCR_TCAPCLK_DIV_6: equ 80h ; MASK: TCAPCLK Divider Value 6
00C0 TMRCLKCR_TCAPCLK_DIV_8: equ C0h ; MASK: TCAPCLK Divider Value 8
0000
0032 CLKIOCR: equ 32h ; Clock I/O Configuration Register (RW)
0000 CLKIOCR_CLKOUT_IOSC: equ 00h ; MASK: Clock Source--Internal Oscillator
0001 CLKIOCR_CLKOUT_XOSC: equ 01h ; MASK: Clock Source--External Oscillator or CLKIN
0002 CLKIOCR_CLKOUT_LPO: equ 02h ; MASK: Clock Source--Low Power Oscillator (32 Khz)
0003 CLKIOCR_CLKOUT_CPUCLK: equ 03h ; MASK: Clock Source--CPUCLK
0004 CLKIOCR_EFTB_DISABLE: equ 04h ; MASK: EFTB Filter Disable (bypass)
0008 CLKIOCR_XOSC_ENABLE: equ 08h ; MASK: External Crystal Oscillator Enable
0010 CLKIOCR_XOSC_SELECT: equ 10h ; MASK: External Crystal Oscillator Select
0000
0000 ; Oscillator Configuration Registers
0034 IOSCTR: equ 34h ; Internal Oscillator Trim Register (R)
0035 XOSCTR: equ 35h ; Crystal Oscillator Trim Register (R)
0036 LPOSCTR: equ 36h ; Low Power Oscillator Trim Register (RW)
0000
0000 ; SPI Configuration/Data Registers
003C SPIDATA: equ 3Ch ; SPI Data Register (RW)
003D SPICR: equ 3Dh ; SPI Configuration Register (RW)
0000
0000 ; USB SIE Configuration/Data Registers
0040 USBCR: equ 40h ; USB Configuration Register (RW)
0041 EP0CNT: equ 41h ; Endpoint 0 Count Register (RW)
0042 EP1CNT: equ 42h ; Endpoint 1 Count Register (RW)
0043 EP2CNT: equ 43h ; Endpoint 2 Count Register (RW)
0044 EP0MODE: equ 44h ; Endpoint 0 Mode Register (RW)
0045 EP1MODE: equ 45h ; Endpoint 1 Mode Register (RW)
0046 EP2MODE: equ 46h ; Endpoint 2 Mode Register (RW)
0050 EP0DATA: equ 50h ; Endpoint 0 Data Register (50h-57h) (RW)
0058 EP1DATA: equ 58h ; Endpoint 1 Data Register (58h-5Fh) (RW)
0060 EP2DATA: equ 60h ; Endpoint 2 Data Register (60h-67h) (RW)
0000
0000 ; Band-gap/TRIMBUF Configuration Registers
0070 BGAPTR: equ 70h ; Band-gap Trim Register (R)
0071 TRIM0: equ 71h ; TRIMBUF Trim Register 0 (R)
0072 TRIM1: equ 72h ; TRIMBUF Trim Register 1 (R)
0000
0000 ; VREG Configuration Register
0073 VREGCR: equ 73h ; VREG Configuration Register (RW)
0000
0000 ; USB Transceiver Configuration Registers
0074 USBXCR: equ 74h ; USB Transceiver Configuration Register (RW)
0080 USBXCR_ENABLE: equ 80h ; USB Transceiver Enable
0001 USBXCR_FORCE: equ 01h ; USB Transceiver Force
0000
0000 ; Data Pointer Registers--Listed for compatability with other M8C based parts.
00D0 CPPDR: equ D0h ; Current Page Pointer Data Register (RW)
00D4 DPRDR: equ D4h ; Data Page Read Register (RW)
00D5 DPWDR: equ D5h ; Data Page Write Register (RW)
0000
0000 ; Watchdog Timer Reset
00E3 RESWDT: equ E3h ; Watchdog Timer Reset (W)
00E3 RES_WDT: equ E3h ; WatchDog Timer Register (W) (PSoC)
0000
0000 ;------------------------------------------------
0000 ; System and Global Resource Registers
0000 ;------------------------------------------------
00DA INT_CLR0: equ DAh ; Interrupt Clear Register 0 (RW)
0000 ; Use INT_MSK0 bit field masks
00DB INT_CLR1: equ DBh ; Interrupt Clear Register 1 (RW)
0000 ; Use INT_MSK1 bit field masks
00DC INT_CLR2: equ DCh ; Interrupt Clear Register 2 (RW)
0000 ; Use INT_MSK2 bit field masks
0000
00DE INT_MSK3: equ DEh ; Interrupt Mask Register (RW)
0080 INT_MSK3_ENSWINT: equ 80h ; MASK: enable/disable SW interrupt
0000
00DF INT_MSK2: equ DFh ; Interrupt Mask Register (RW)
0040 INT_MSK2_GPIO_PORT4: equ 40h ; MASK: enable/disable GPIO Port 4 interrupt
0020 INT_MSK2_GPIO_PORT3: equ 20h ; MASK: enable/disable GPIO Port 3 interrupt
0010 INT_MSK2_GPIO_PORT2: equ 10h ; MASK: enable/disable GPIO Port 2 interrupt
0008 INT_MSK2_PS2_DATA_LOW: equ 08h ; MASK: enable/disable PS/2 Data Low
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