?? psocconfigtbl.lis
字號:
0004 INT_MSK2_GPIO_INT2: equ 04h ; MASK: enable/disable GPIO INT2 interrupt
0002 INT_MSK2_CTR_16_WRAP: equ 02h ; MASK: enable/disable 16 bit counter wrap
0001 INT_MSK2_TCAP1: equ 01h ; MASK: enable/disable Timer/Capture 0 interrupt
0000
00E0 INT_MSK0: equ E0h ; Interrupt Mask Register (RW)
0080 INT_MSK0_GPIO_PORT1: equ 80h ; MASK: enable/disable GPIO Port 1 interrupt
0040 INT_MSK0_SLEEP: equ 40h ; MASK: enable/disable sleep interrupt
0020 INT_MSK0_GPIO_INT1: equ 20h ; MASK: enable/disable GPIO INT1 interrupt
0010 INT_MSK0_GPIO_PORT0: equ 10h ; MASK: enable/disable GPIO Port 0 interrupt
0008 INT_MSK0_SPI_RX: equ 08h ; MASK: enable/disable SPI Receive interrupt
0004 INT_MSK0_SPI_TX: equ 04h ; MASK: enable/disable SPI Transmit interrupt
0002 INT_MSK0_GPIO_INT0: equ 02h ; MASK: enable/disable GPIO INT0 interrupt
0001 INT_MSK0_POR_LVD: equ 01h ; MASK: enable/disable POR/LVD interrupt
0000
00E1 INT_MSK1: equ E1h ; Interrupt Mask Register (RW)
0080 INT_MSK1_TCAP0: equ 80h ; MASK: enable/disable Timer/Capture 0 interrupt
0040 INT_MSK1_PIT: equ 40h ; MASK: enable/disable Progrmmable Interval Timer
0020 INT_MSK1_MS_TIMER: equ 20h ; MASK: enable/disable One Millisecond Timer interrupt
0010 INT_MSK1_USB_ACTIVITY: equ 10h ; MASK: enable/disable USB Bus Activity interrupt
0008 INT_MSK1_USB_BUS_RESET: equ 08h ; MASK: enable/disable USB Bus Reset interrupt
0004 INT_MSK1_USB_EP2: equ 04h ; MASK: enable/disable USB Endpoint 2 interrupt
0002 INT_MSK1_USB_EP1: equ 02h ; MASK: enable/disable USB Endpoint 1 interrupt
0001 INT_MSK1_USB_EP0: equ 01h ; MASK: enable/disable USB Endpoint 0 interrupt
0000
00E2 INT_VC: equ E2h ; Interrupt vector register (RC)
0000
0000 ;------------------------------------------------------
0000 ; System Status and Control Registers
0000 ;------------------------------------------------------
0000 ; Register bank 1.
0000 ;------------------------------------------------------
00E0 OSC_CR0: equ E0h ; System Oscillator Control Register 0 (RW)
0020 OSC_CR0_NO_BUZZ: equ 20h ; MASK: Bandgap always powered/BUZZ bandgap
0018 OSC_CR0_SLEEP: equ 18h ; MASK: Set Sleep timer freq/period
0000 OSC_CR0_SLEEP_512Hz: equ 00h ; Set sleep bits for 1.95ms period
0008 OSC_CR0_SLEEP_64Hz: equ 08h ; Set sleep bits for 15.6ms period
0010 OSC_CR0_SLEEP_8Hz: equ 10h ; Set sleep bits for 125ms period
0018 OSC_CR0_SLEEP_1Hz: equ 18h ; Set sleep bits for 1 sec period
0000
0007 OSC_CR0_CPU: equ 07h ; MASK: Set CPU Frequency
0000 OSC_CR0_CPU_3MHz: equ 00h ; set CPU Freq bits for 3MHz Operation
0001 OSC_CR0_CPU_6MHz: equ 01h ; set CPU Freq bits for 6MHz Operation
0002 OSC_CR0_CPU_12MHz: equ 02h ; set CPU Freq bits for 12MHz Operation
0003 OSC_CR0_CPU_24MHz: equ 03h ; set CPU Freq bits for 24MHz Operation
0004 OSC_CR0_CPU_1d5MHz: equ 04h ; set CPU Freq bits for 1.5MHz Operation
0005 OSC_CR0_CPU_750kHz: equ 05h ; set CPU Freq bits for 750kHz Operation
0006 OSC_CR0_CPU_187d5kHz: equ 06h ; set CPU Freq bits for 187.5kHz Operation
0000
0000 ;------------------------------------------------------
0000 ; Note: The following registers are mapped into both
0000 ; register bank 0 AND register bank 1.
0000 ;------------------------------------------------------
00F7 CPU_F: equ F7h ; CPU Flag Register Access (RO)
0000 ; Use FLAG_ masks defined at top of file
00FF CPU_SCR: equ FFh ; CPU Status and Control Register (#)
0080 CPU_SCR_GIE_MASK: equ 80h ; MASK: Global Interrupt Enable shadow
0020 CPU_SCR_WDRS_MASK: equ 20h ; MASK: Watch Dog Timer Reset
0010 CPU_SCR_PORS_MASK: equ 10h ; MASK: power-on reset bit PORS
0008 CPU_SCR_SLEEP_MASK: equ 08h ; MASK: Enable Sleep
0001 CPU_SCR_STOP_MASK: equ 01h ; MASK: Halt CPU bit
0000
0000 ;;=============================================================================
0000 ;; Register Space, Bank 1
0000 ;;=============================================================================
0000
0000 ;------------------------------------------------
0000 ; Clock and System Control Registers
0000 ;------------------------------------------------
0000
0000 ;;=============================================================================
0000 ;; M8C System Macros
0000 ;; These macros should be used when their functions are needed.
0000 ;;=============================================================================
0000
0000 ;----------------------------------------------------
0000 ; Swapping Register Banks
0000 ;----------------------------------------------------
0000 macro M8C_SetBank0
0000 and F, ~FLAG_XIO_MASK
0000 macro M8C_SetBank1
0000 or F, FLAG_XIO_MASK
0000 macro M8C_EnableGInt
0000 or F, FLAG_GLOBAL_IE
0000 macro M8C_DisableGInt
0000 and F, ~FLAG_GLOBAL_IE
0000 macro M8C_DisableIntMask
0000 and reg[@0], ~@1 ; disable specified interrupt enable bit
0000 macro M8C_EnableIntMask
0000 or reg[@0], @1 ; enable specified interrupt enable bit
0000 macro M8C_ClearIntFlag
0000 mov reg[@0], ~@1 ; clear specified interrupt enable bit
0000 macro M8C_EnableWatchDog
0000 and reg[CPU_SCR], ~CPU_SCR_PORS_MASK
0000 macro M8C_ClearWDT
0000 mov reg[RES_WDT], 00h
0000 macro M8C_ClearWDTAndSleep
0000 mov reg[RES_WDT], 38h
0000 macro M8C_Sleep
0000 or reg[CPU_SCR], CPU_SCR_SLEEP_MASK
0000 ; The next instruction to be executed depends on the state of the
0000 ; various interrupt enable bits. If some interrupts are enabled
0000 ; and the global interrupts are disabled, the next instruction will
0000 ; be the one that follows the invocation of this macro. If global
0000 ; interrupts are also enabled then the next instruction will be
0000 ; from the interrupt vector table. If no interrupts are enabled
0000 ; then the CPU sleeps forever.
0000 macro M8C_Stop
0000 ; In general, you probably don't want to do this, but here's how:
0000 or reg[CPU_SCR], CPU_SCR_STOP_MASK
0000 ; Next instruction to be executed is located in the interrupt
0000 ; vector table entry for Power-On Reset.
0000 macro M8C_Reset
0000 ; Restore CPU to the power-on reset state.
0000 mov A, 0
0000 SSC
0000 ; Next non-supervisor instruction will be at interrupt vector 0.
0000 macro Suspend_CodeCompressor
0000 or F, 0
0000 macro Resume_CodeCompressor
0000 add SP, 0
export LoadConfigTBL_drawusb2
AREA psoc_config(rom, rel)
0000 LoadConfigTBL_drawusb2:
0000 ; Ordered Global Register values
0000 70EF and F, ~FLAG_XIO_MASK
0002 ; Global Register values
0002 623000 mov reg[30h], 00h ; CPUCLKCR register (CPUCLKCR)
0005 620500 mov reg[05h], 00h ; P00CR register (P00CR)
0008 620600 mov reg[06h], 00h ; P01CR register (P01CR)
000B 620706 mov reg[07h], 06h ; P02CR register (P02CR)
000E 620806 mov reg[08h], 06h ; P03CR register (P03CR)
0011 620900 mov reg[09h], 00h ; P04CR register (P04CR)
0014 620A07 mov reg[0ah], 07h ; P05CR register (P05CR)
0017 620B07 mov reg[0bh], 07h ; P06CR register (P06CR)
001A 620C00 mov reg[0ch], 00h ; P07CR register (P07CR)
001D 620D00 mov reg[0dh], 00h ; P10CR register (P10CR)
0020 620E00 mov reg[0eh], 00h ; P11CR register (P11CR)
0023 620F00 mov reg[0fh], 00h ; P12CR register (P12CR)
0026 621000 mov reg[10h], 00h ; P13CR register (P13CR)
0029 621100 mov reg[11h], 00h ; P14CR register (P14CR)
002C 621200 mov reg[12h], 00h ; P15CR register (P15CR)
002F 621300 mov reg[13h], 00h ; P16CR register (P16CR)
0032 621400 mov reg[14h], 00h ; P17CR register (P17CR)
0035 621500 mov reg[15h], 00h ; P20CR register (P20CR)
0038 621600 mov reg[16h], 00h ; P30CR register (P30CR)
003B 621700 mov reg[17h], 00h ; P40CR register (P40CR)
003E 623D00 mov reg[3dh], 00h ; SPICR register (SPICR)
0041 622B00 mov reg[2bh], 00h ; TCAPINTE register (TCAPINTE)
0044 623100 mov reg[31h], 00h ; TMRCLKCR register (TMRCLKCR)
0047 622A00 mov reg[2ah], 00h ; TMRCR register (TMRCR)
004A 627300 mov reg[73h], 00h ; VREGCR register (VREGCR)
004D ; Instance name USB, User Module USB
004D 7110 or F, FLAG_XIO_MASK
004F ; Global Register values
004F 62E314 mov reg[e3h], 14h ; VLDCR register (VLDCR)
0052 ; Instance name USB, User Module USB
0052 70EF and F, ~FLAG_XIO_MASK
0054 7F ret
0055
0055
0055 ; PSoC Configuration file trailer PsocConfig.asm
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