?? boot.lis
字號:
0000 ; Generated by PSoC Designer ver 4.4 b1884 : 14 Jan, 2007
0000 ;
0000 ;@Id: boot.tpl#238 @
0000 ;=============================================================================
0000 ; FILENAME: boot.asm
0000 ; VERSION: 4.07
0000 ; DATE: 9 March 2005
0000 ;
0000 ; DESCRIPTION:
0000 ; M8C Boot Code for CY7C63900 microcontroller family.
0000 ; This file also contains the Interrupt Service Routines for enCoRe II GPIO
0000 ; interrupts: INT0, INT1, INT2, as well as the GPIO Port interrupts for
0000 ; port 0, port 1, port 2, port 3 and port 4.
0000 ;
0000 ; Copyright (C) Cypress Semiconductor 2004, 2005. All rights reserved.
0000 ;
0000 ; NOTES:
0000 ; PSoC Designer's Device Editor uses a template file, BOOT.TPL, located in
0000 ; the project's root directory to create BOOT.ASM. Any changes made to
0000 ; BOOT.ASM will be overwritten every time the project is generated; therfore
0000 ; changes should be made to BOOT.TPL not BOOT.ASM. Care must be taken when
0000 ; modifying BOOT.TPL so that replacement strings (such as @PROJECT_NAME)
0000 ; are not accidentally modified.
0000 ;
0000 ;=============================================================================
0000
0000 CPU_CLOCK: equ 0h ;CPU Clock value
0001 CPU_CLOCK_MASK: equ 1h ;CPU Clock mask
0000 CPU_CLOCK_JUST: equ 0h ;CPU Clock value justified
0000
0003 CPU_CLOCK_SPEED: equ 3h ;CPU Clock Speed value
0007 CPU_CLOCK_SPEED_MASK: equ 7h ;CPU Clock Speed mask
0003 CPU_CLOCK_SPEED_JUST: equ 3h ;CPU Clock Speed value justified
0000
0000 TIMER_CLOCK: equ 0h ;Timer Clock value
0003 TIMER_CLOCK_MASK: equ 3h ;Timer Clock mask
0000 TIMER_CLOCK_JUST: equ 0h ;Timer Clock value justified
0000
0000 TIMER_CLOCK_SPEED: equ 0h ;Timer clock speed value
000C TIMER_CLOCK_SPEED_MASK: equ ch ;Timer clock speed mask
0000 TIMER_CLOCK_SPEED_JUST: equ 0h ;Timer clock speed value justified
0000
0000 CAPT_CLOCK: equ 0h ;Capture Clock value
0030 CAPT_CLOCK_MASK: equ 30h ;Capture Clock mask
0000 CAPT_CLOCK_JUST: equ 0h ;Capture Clock value justified
0000
0000 CAPT_CLOCK_SPEED: equ 0h ;Capture Clock speed value
00C0 CAPT_CLOCK_SPEED_MASK: equ c0h ;Capture Clock speed mask
0000 CAPT_CLOCK_SPEED_JUST: equ 0h ;Capture Clock speed value justified
0000
0000 CAPT_EDGE: equ 0h ;Capture Edge value
0080 CAPT_EDGE_MASK: equ 80h ;Capture Edge mask
0000 CAPT_EDGE_JUST: equ 0h ;Capture Edge value justified
0000
0000 CAPT_PRESCALE: equ 0h ;Capture Prescale value
0070 CAPT_PRESCALE_MASK: equ 70h ;Capture Prescale mask
0000 CAPT_PRESCALE_JUST: equ 0h ;Capture Prescale value justified
0000
0000 USB_CLOCK: equ 0h ;USB Clock source value
0020 USB_CLOCK_MASK: equ 20h ;USB Clock source mask
0000 USB_CLOCK_JUST: equ 0h ;USB Clock source justified
0000
0000 USB_CLOCK_SPEED: equ 0h ;USB Clock div by 2 value
0040 USB_CLOCK_SPEED_MASK: equ 40h ;USB Clock div by 2 mask
0000 USB_CLOCK_SPEED_JUST: equ 0h ;USB Clock div by 2 justified
0000
0000 CLOCK_OUT: equ 0h ;Clock Out value
0003 CLOCK_OUT_MASK: equ 3h ;Clock Out mask
0000 CLOCK_OUT_JUST: equ 0h ;Clock Out value justified
0000
0000 EFTB: equ 0h ;EFTB value
0004 EFTB_MASK: equ 4h ;EFTB mask
0000 EFTB_JUST: equ 0h ;EFTB value justified
0000
0000 XOSC_ENABLE: equ 0h ;Crystal Osc value
0008 XOSC_ENABLE_MASK: equ 8h ;Crystal Osc mask
0000 XOSC_ENABLE_JUST: equ 0h ;Crystal Osc value justified
0000
0000 XOSC_XGM: equ 0h ;Crystal Osc Xgm value
001C XOSC_XGM_MASK: equ 1ch ;Crystal Osc Xgm mask
0000 XOSC_XGM_JUST: equ 0h ;Crystal Osc Xgm value justified
0000
0004 LV_DETECT_LEVEL: equ 4h ;Low V Detect Level value
0007 LV_DETECT_LEVEL_MASK: equ 7h ;Low V Detect Level mask
0004 LV_DETECT_LEVEL_JUST: equ 4h ;Low V Detect Level value justified
0000
0001 PWR_ON_RESET_LEVEL: equ 1h ;PowerOn Reset Level value
0030 PWR_ON_RESET_LEVEL_MASK: equ 30h ;PowerOn Reset Level mask
0010 PWR_ON_RESET_LEVEL_JUST: equ 10h ;PowerOn Reset Level value justified
0000
0000 VREG_ENABLE: equ 0h ;VREG Enable value
0001 VREG_ENABLE_MASK: equ 1h ;VREG Enable mask
0000 VREG_ENABLE_JUST: equ 0h ;VREG Enable value justified
0000
0000 KEEP_ALIVE: equ 0h ;Keep Alive value
0002 KEEP_ALIVE_MASK: equ 2h ;Keep Alive mask
0000 KEEP_ALIVE_JUST: equ 0h ;Keep Alive value justified
0000
0000 WATCHDOG_ENABLE: equ 0h ;Watchdog Enable value
0010 FLAG_XIO_MASK: equ 10h
0008 FLAG_SUPER: equ 08h
0004 FLAG_CARRY: equ 04h
0002 FLAG_ZERO: equ 02h
0001 FLAG_GLOBAL_IE: equ 01h
0000
0000 ;;=============================================================================
0000 ;; Register Space, Bank 0
0000 ;;=============================================================================
0000
0000 ;------------------------------------------------
0000 ; Port Registers
0000 ;------------------------------------------------
0000 ; Port Data Registers
0000 P0DATA: equ 00h ; Port 0 Data Register (RW)
0001 P1DATA: equ 01h ; Port 1 Data Register (RW)
0002 P2DATA: equ 02h ; Port 2 Data Register (RW)
0003 P3DATA: equ 03h ; Port 3 Data Register (RW)
0004 P4DATA: equ 04h ; Port 4 Data Register (RW)
0000 ; PSoC Compatability
0000 PRT0DR: equ 00h ; Port 0 Data Register (RW)(PSoC)
0001 PRT1DR: equ 01h ; Port 1 Data Register (RW)(PSoC)
0002 PRT2DR: equ 02h ; Port 2 Data Register (RW)(PSoC)
0003 PRT3DR: equ 03h ; Port 3 Data Register (RW)(PSoC)
0004 PRT4DR: equ 04h ; Port 4 Data Register (RW)(PSoC)
0000
0000 ; Port/Pin Configuration Registers
0005 P00CR: equ 05h ; P0.0 Configuration Register (RW)
0006 P01CR: equ 06h ; P0.1 Configuration Register (RW)
0007 P02CR: equ 07h ; P0.2 Configuration Register (RW)
0008 P03CR: equ 08h ; P0.3 Configuration Register (RW)
0009 P04CR: equ 09h ; P0.4 Configuration Register (RW)
000A P05CR: equ 0Ah ; P0.5 Configuration Register (RW)
000B P06CR: equ 0Bh ; P0.6 Configuration Register (RW)
000C P07CR: equ 0Ch ; P0.7 Configuration Register (RW)
000D P10CR: equ 0Dh ; P1.0 Configuration Register (RW)
000E P11CR: equ 0Eh ; P1.1 Configuration Register (RW)
000F P12CR: equ 0Fh ; P1.2 Configuration Register (RW)
0010 P13CR: equ 10h ; P1.3 Configuration Register (RW)
0011 P14CR: equ 11h ; P1.4 Configuration Register (RW)
0012 P15CR: equ 12h ; P1.5 Configuration Register (RW)
0013 P16CR: equ 13h ; P1.6 Configuration Register (RW)
0014 P17CR: equ 14h ; P1.7 Configuration Register (RW)
0015 P2CR: equ 15h ; P2.0-P2.7 Configuration Register (RW)
0016 P3CR: equ 16h ; P3.0-P3.7 Configuration Register (RW)
0017 P4CR: equ 17h ; P4.0-P4.7 Configuration Register (RW)
0000
0000 ; Timer Registers
0020 FRTMRL: equ 20h ; Free Running Timer Low (RW)
0021 FRTMRH: equ 21h ; Free Running Timer High (RW)
0022 TCAP0R: equ 22h ; Capture 0 Rising (R)
0023 TCAP1R: equ 23h ; Capture 1 Rising (R)
0024 TCAP0F: equ 24h ; Capture 0 Falling (R)
0025 TCAP1F: equ 25h ; Capture 1 Falling (R)
0026 PITMRL: equ 26h ; Programmable Interval Timer Low (RW)
0027 PITMRH: equ 27h ; Programmable Interval Timer High (RW)
0028 PIRL: equ 28h ; Programmable Interval Timer Reload Low (RW)
0029 PIRH: equ 29h ; Programmable Interval Timer Reload High (RW)
002A TMRCR: equ 2Ah ; Timer Configuration Register (RW)
002B TCAPINTE: equ 2Bh ; Capture Timer Interrupt Enable (RW)
002C TCAPINTS: equ 2Ch ; Capture Timer Interrupt Status (RW)
0000
0000 ; Clock Configuration Registers
0030 CPUCLKCR: equ 30h ; CPU Clock Configuration Register (RW)
0000 CPUCLK_SEL_INT: equ 00h ; CPU Clock Select Internal Oscillator
0001 CPUCLK_SEL_EXT: equ 01h ; CPU Clock Select External Clock
0000 CPUCLK_USBCLK_SEL_INT: equ 00h ; USB Clock Select Internal Clock
0040 CPUCLK_USBCLK_SEL_EXT: equ 40h ; USB Clock Select External Clock
0000 CPUCLK_USBCLK_DIV2_DIS: equ 00h ; USB Clock Divide by 2 disable
0080 CPUCLK_USBCLK_DIV2_ENA: equ 80h ; USB Clock Divide by 2 enable
0000
0031 TMRCLKCR: equ 31h ; Timer Clock Configuration Register (RW)
0000 TMRCLKCR_ITMRCLK_IOSC: equ 00h ; MASK: ITMRCLK Source--Internal Oscillator
0001 TMRCLKCR_ITMRCLK_XOSC: equ 01h ; MASK: ITMRCLK Source--External Oscillator or CLKIN
0002 TMRCLKCR_ITMRCLK_LPO: equ 02h ; MASK: ITMRCLK Source--Low Power Oscillator (32 Khz)
0003 TMRCLKCR_ITMRCLK_TCAPCLK: equ 03h ; MASK: ITMRCLK Source--TCAPCLK
0000 TMRCLKCR_ITMRCLK_DIV_1: equ 00h ; MASK: ITMRCLK Divider Value 1
0004 TMRCLKCR_ITMRCLK_DIV_2: equ 04h ; MASK: ITMRCLK Divider Value 2
0008 TMRCLKCR_ITMRCLK_DIV_3: equ 08h ; MASK: ITMRCLK Divider Value 3
000C TMRCLKCR_ITMRCLK_DIV_4: equ 0Ch ; MASK: ITMRCLK Divider Value 4
0002 TMRCLKCR_ITMRCLK_LPO: equ 02h ; MASK: ITMRCLK Source--Low Power Oscillator (32 Khz)
0000 TMRCLKCR_TCAPCLK_IOSC: equ 00h ; MASK: TCAPCLK Source--Internal Oscillator
0010 TMRCLKCR_TCAPCLK_XOSC: equ 10h ; MASK: TCAPCLK Source--External Oscillator or CLKIN
0020 TMRCLKCR_TCAPCLK_LPO: equ 20h ; MASK: TCAPCLK Source--Low Power Oscillator (32 Khz)
0030 TMRCLKCR_TCAPCLK_DISABLED: equ 30h ; MASK: TCAPCLK Source--DISABLED
0000 TMRCLKCR_TCAPCLK_DIV_2: equ 00h ; MASK: TCAPCLK Divider Value 2
0040 TMRCLKCR_TCAPCLK_DIV_4: equ 40h ; MASK: TCAPCLK Divider Value 4
0080 TMRCLKCR_TCAPCLK_DIV_6: equ 80h ; MASK: TCAPCLK Divider Value 6
00C0 TMRCLKCR_TCAPCLK_DIV_8: equ C0h ; MASK: TCAPCLK Divider Value 8
0000
0032 CLKIOCR: equ 32h ; Clock I/O Configuration Register (RW)
0000 CLKIOCR_CLKOUT_IOSC: equ 00h ; MASK: Clock Source--Internal Oscillator
0001 CLKIOCR_CLKOUT_XOSC: equ 01h ; MASK: Clock Source--External Oscillator or CLKIN
0002 CLKIOCR_CLKOUT_LPO: equ 02h ; MASK: Clock Source--Low Power Oscillator (32 Khz)
0003 CLKIOCR_CLKOUT_CPUCLK: equ 03h ; MASK: Clock Source--CPUCLK
0004 CLKIOCR_EFTB_DISABLE: equ 04h ; MASK: EFTB Filter Disable (bypass)
0008 CLKIOCR_XOSC_ENABLE: equ 08h ; MASK: External Crystal Oscillator Enable
0010 CLKIOCR_XOSC_SELECT: equ 10h ; MASK: External Crystal Oscillator Select
0000
0000 ; Oscillator Configuration Registers
0034 IOSCTR: equ 34h ; Internal Oscillator Trim Register (R)
0035 XOSCTR: equ 35h ; Crystal Oscillator Trim Register (R)
0036 LPOSCTR: equ 36h ; Low Power Oscillator Trim Register (RW)
0000
0000 ; SPI Configuration/Data Registers
003C SPIDATA: equ 3Ch ; SPI Data Register (RW)
003D SPICR: equ 3Dh ; SPI Configuration Register (RW)
0000
0000 ; USB SIE Configuration/Data Registers
0040 USBCR: equ 40h ; USB Configuration Register (RW)
0041 EP0CNT: equ 41h ; Endpoint 0 Count Register (RW)
0042 EP1CNT: equ 42h ; Endpoint 1 Count Register (RW)
0043 EP2CNT: equ 43h ; Endpoint 2 Count Register (RW)
0044 EP0MODE: equ 44h ; Endpoint 0 Mode Register (RW)
0045 EP1MODE: equ 45h ; Endpoint 1 Mode Register (RW)
0046 EP2MODE: equ 46h ; Endpoint 2 Mode Register (RW)
0050 EP0DATA: equ 50h ; Endpoint 0 Data Register (50h-57h) (RW)
0058 EP1DATA: equ 58h ; Endpoint 1 Data Register (58h-5Fh) (RW)
0060 EP2DATA: equ 60h ; Endpoint 2 Data Register (60h-67h) (RW)
0000
0000 ; Band-gap/TRIMBUF Configuration Registers
0070 BGAPTR: equ 70h ; Band-gap Trim Register (R)
0071 TRIM0: equ 71h ; TRIMBUF Trim Register 0 (R)
0072 TRIM1: equ 72h ; TRIMBUF Trim Register 1 (R)
?? 快捷鍵說明
復(fù)制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -