//Demonstration of simple buffered SCI

#include <hidef.h>      /* common defines and macros */
#include <mc9s12xdt512.h>     /* derivative information */
#include "xgate.h"
#pragma LINK_INFO DERIVATIVE "mc9s12xdt512"


#include <string.h>
#include "xgate.h"

#define REFDVNUMBER 15

extern tBuffer Buffer0;
interrupt void SCI_ISR();

/************************* Macros ******************************************/

#define ROUTE_INTERRUPT(vec_adr, cfdata)                \
  INT_CFADDR= (vec_adr) & 0xF0;                         \
  INT_CFDATA_ARR[((vec_adr) & 0x0F) >> 1]= (cfdata)

#define SCI0_VEC  0xD6 /* vector address= $xxD6 */


//Initialise the XGATE
static void SetupXGATE(void)
{
  /* initialize the XGATE vector block and
     set the XGVBR register to its start address */
  XGVBR= (unsigned int)(void*__far)(XGATE_VectorTable - XGATE_VECTOR_OFFSET);

  /* switch SCI0 interrupt to XGATE */
  ROUTE_INTERRUPT(SCI0_VEC, 0x81); /* RQST=1 and PRIO=1 */

  /* enable XGATE mode and interrupts */
  XGMCTL= 0xFBC1; /* XGE | XGFRZ | XGIE */
}

/******************************************************************************
Function Name	:	PLLStartup
Engineer		:	r27624
Date			:	26/9/2001
                :   7/15/2008 copy from the MSCAN demo by ChenXi
Arguments		:	freq: 
Return			:	
Notes			:	Ref Clock is assumed to be 1MHz
******************************************************************************/
void PLLStartup(unsigned char freq) 
{
	/* switch to OSCCLK */
	//--CRG.clksel.byte = 0;
    CLKSEL = 0;
 	//--CRG.pllctl.byte = CME   |		/* clock monitor enabled */
  	//--                PLLON |		/* PLL on */
	//--                  AUTO	|		/* automatic bandwidth control enabled */
	//--	                SCME;			/* self clock mode enabled */
	PLLCTL = PLLCTL_CME_MASK | PLLCTL_PLLON_MASK | PLLCTL_AUTO_MASK | PLLCTL_SCME_MASK;
	if(freq != 0) 
	{
	  	/* configure PLL */
		/* fref = fosc / (REFDV+1) */
  		//--CRG.refdv.byte = REFDV;
  		REFDV = REFDVNUMBER;
		/* fvco = 2*fref*(SYNR0+1) */
  		//--CRG.synr.byte = freq - 1;
  		SYNR = freq-1;
		/* wait for lock FOR EVER! */
  		//--while(CRG.crgflg.bit.lock != 1) 
  		while(CRGFLG_LOCK != 1)
  		{
  		}
	  	//--if(CRG.crgflg.bit.lock == 1) 
	  	if(CRGFLG_LOCK == 1)
	  	{
									/* switch to PLLCLK */
	    	//--CRG.clksel.byte |= PLLSEL;
	    	CLKSEL |= CLKSEL_PLLSEL_MASK;
  		}
	}
}

void main(void)
{
  /* put your own code here */
  PLLStartup(40);
  EnableInterrupts;
  SetupXGATE();
  
  //Initial first SCI Buffer
  Buffer0.size = 4;
  Buffer0.character[0]='1';
  Buffer0.character[1]='2';
  Buffer0.character[2]='3';
  Buffer0.character[3]=' ';
  
  //Configure baudrate = 19200 at 25MHz
//--  SCI0BD = 81;
  //Configure baudrate = 19200 at 40MHz
  SCI0BD = 130;
  //Enable transmitter
  SCI0CR2_TE = 1;

  /* Enable the SCI Tx interrupt to start the transfer */
  SCI0CR2_SCTIE = 1;

  for(;;) {} /* wait forever */
  /* please make sure that you never leave this function */
}

#pragma CODE_SEG __NEAR_SEG NON_BANKED 

//CPU Interrupt generated by XGATE when SIMPLE is not defined - see xgate.cxgate file
interrupt void SCI_Handler()
{
  unsigned char temp;
  //Clear XGATE interrupt flag - SCI0 is channel $6B
  XGIF1 = 0x0800;

  //Initialise buffer with new values
  Buffer0.size = 4;
  temp = Buffer0.character[0];
  Buffer0.character[0] = Buffer0.character[1];
  Buffer0.character[1] = Buffer0.character[2];
  Buffer0.character[2] = temp;
  
  /* Enable the SCI Tx interrupt to start the transfer */
  SCI0CR2_SCTIE = 1;
}