// Read device's configuration header (except for device-specific information) 
            Length = HalGetBusData(PCIConfiguration, Bus, SlotNumber.u.AsULONG, &Cfg, sizeof(Cfg) - sizeof(Cfg.DeviceSpecific));

            if (Length != (sizeof(Cfg) - sizeof(Cfg.DeviceSpecific)) ||
                (Cfg.DeviceID == PCI_INVALID_DEVICEID) || (Cfg.VendorID == PCI_INVALID_VENDORID) || (Cfg.VendorID == 0)) {
                // No function found
                if (Function != 0) {
                    // If a multi-function device, continue to next function
                    continue;
                } else {
                    // If not a multi-function device, continue to next device
                    break;
                }
            }

            switch (Cfg.HeaderType & ~PCI_MULTIFUNCTION) {
            case PCI_DEVICE_TYPE:  // Device   
                if (!PCICfgDevice(pBusInfo, Bus, Device, Function, &Cfg, pMemSize, pIoSize, pPrefetchMemSize)) {
                    RetVal = FALSE;
                }

                break;

            case PCI_BRIDGE_TYPE:  // PCI-PCI bridge
                if (!PCICfgBridge(pBusInfo, Bus, Device, Function, &Cfg, pSubordinateBus, pMemSize, pIoSize, pPrefetchMemSize)) {
                    RetVal = FALSE;
                }

                break;

            case PCI_CARDBUS_TYPE:  // PCI-Cardbus bridge
                if (!PCICfgCardBusBridge(pBusInfo, Bus, Device, Function, &Cfg,pSubordinateBus, pMemSize, pIoSize)) {
                    RetVal = FALSE;
                }

                break;

            default:
                DEBUGMSG(ZONE_ERROR, (L"PCIBUS!PCICfgBus: Invalid HeaderType, 0x%X, found for Device %d/%d/%d\r\n",
                    Cfg.HeaderType, Bus, Device, Function));
            }

            if (Function == 0 && !(Cfg.HeaderType & PCI_MULTIFUNCTION)) {
                // Not a multifunction device, continue on to next device
                break;
            }
        }
    }

    DEBUGMSG(ZONE_INIT, (L"PCIBUS!PCICfgBus-(Bus %d, SubBus %d, MemSize 0x%X, IoSize 0x%X, PrefetchMemSize=0x%X)\r\n", Bus, *pSubordinateBus, *pMemSize, *pIoSize, 
        pPrefetchMemSize!=NULL?*pPrefetchMemSize:0));
    
    return RetVal;
}


//
// Initialize and configure device
//
static BOOL
PCICfgDevice(
    PPCI_DEV_INFO pBusInfo,
    ULONG Bus,
    ULONG Device,
    ULONG Function,
    PPCI_COMMON_CONFIG pCfg,
    PULONG pMemSize,
    PULONG pIoSize,
    PULONG pPrefetchMemSize
    )
{
    DWORD Reg;
    PCI_DEV_INFO Info;
    
    DEBUGMSG(ZONE_FUNCTION, (L"PCIBUS!PCICfgDevice+(Bus %d, Device %d, Function %d, Vendor ID 0x%X, Device ID 0x%X)\r\n",
        Bus, Device, Function, pCfg->VendorID, pCfg->DeviceID));

    // Initialize Info structure
    PCIInitInfo(pBusInfo->RegPath, Bus, Device, Function, pCfg, &Info);

    // Attempt to find match for this device in the registry and get info
    if (PCICfgFindMatch(&Info)) {
        Info.Matched = TRUE;

        if (!RegGetInfo(&Info)) {
            return FALSE;
        }
        if ( (Info.DevFlags & DEVFLAGS_BOOTPHASE_1 ) && !IsSystemPhase1()) {
            DEBUGMSG(ZONE_WARNING, (L"PCIBUS!PCICfgDevice: Registry says only configure this device in phase 1\r\n"));
            // Do not load driver that set only loaded on phase 1.
            return TRUE;
        }

        if (!Info.Configure) {
            // If instructed not to configure, disable device and return
            DEBUGMSG(ZONE_WARNING, (L"PCIBUS!PCICfgDevice: Registry says don't configure this device\r\n"));

            if (pCfg->Command & (PCI_ENABLE_IO_SPACE | PCI_ENABLE_MEMORY_SPACE | PCI_ENABLE_BUS_MASTER)) {
                PCIConfig_Write(Bus, Device, Function, PCI_CONFIG_COMMAND_STATUS, 0xFFFF0000);
            }
            
            return TRUE;
        }

        // Make sure the sum of Base entries is less than or equal to 6
        if (Info.MemBase.Num + Info.IoBase.Num > PCI_TYPE0_ADDRESSES) {
            DEBUGMSG(ZONE_ERROR, (L"PCIBUS!PCICfgDevice: The number of registry values '%s' and '%s' under '%s' must sum to be less than %d.\r\n",
                PCIBUS_MEMBASE_VALNAME, PCIBUS_IOBASE_VALNAME, Info.RegPath, PCI_TYPE0_ADDRESSES));

            return FALSE;
        }

        // Make sure the sum of Len entries is less than or equal to 6
        if (Info.MemLen.Num + Info.IoLen.Num > PCI_TYPE0_ADDRESSES) {
            DEBUGMSG(ZONE_ERROR, (L"PCIBUS!PCICfgDevice: The number of registry values '%s' and '%s' under '%s' must sum to be less than %d.\r\n",
                PCIBUS_MEMLEN_VALNAME, PCIBUS_IOLEN_VALNAME, Info.RegPath, PCI_TYPE0_ADDRESSES));

            return FALSE;
        }
    }
    else {
#ifdef DEBUG
        if (ZONE_WARNING) {
            RETAILMSG(1,(TEXT("Warning: No Match template is found for following PCI Device\r\n")));
            DumpPciConfig(&Info);
        }
#endif    
    }
    // If ConfigEntry defined, call it instead of CheckBARs
    if (Info.ConfigEntry) {
        DWORD Status;
        
        // Load driver Dll and obtain ConfigEntry function address
        if (!LoadConfigEntry(&Info)) {
            DEBUGMSG(ZONE_ERROR, (L"PCIBUS!PCICfgDevice: Failed LoadConfigEntry call\r\n"));

            return FALSE;
        }

        Status = ((PFN_CONFIGENTRY)(Info.ConfigInfo->ConfigEntryFn))(PCIBUS_CONFIG_RSRC, &Info, g_MemHead, g_IoHead, pMemSize, pIoSize);
        
        if (Status != ERROR_SUCCESS) {
            if (Status == ERROR_NOT_SUPPORTED) {
                // ConfigEntry point doesn't support this type of call, so do it here
                // Read the base address registers to determine space to allocate
                if (!PCICfgCheckBARs(&Info, pMemSize, pIoSize,pPrefetchMemSize)) {
                    DEBUGMSG(ZONE_ERROR, (L"PCIBUS!PCICfgDevice: Failed PCICfgCheckBARs call\r\n"));
                    
                    return FALSE;
                }
            } else {
                DEBUGMSG(ZONE_ERROR, (L"PCIBUS!PCICfgDevice: Failed %s:%s call\r\n", Info.DllName, Info.ConfigEntryName));

                return FALSE;
            }
        }
    } else {
        // Read the base address registers to determine space to allocate
        if (!PCICfgCheckBARs(&Info, pMemSize, pIoSize,pPrefetchMemSize)) {
            DEBUGMSG(ZONE_ERROR, (L"PCIBUS!PCICfgDevice: Failed PCICfgCheckBARs call\r\n"));
            
            return FALSE;
        }
    }

    // If device not already placed, configure interrupt
    if (!(pCfg->Command & (PCI_ENABLE_IO_SPACE | PCI_ENABLE_MEMORY_SPACE))) {
        DEVICE_LOCATION DevLoc;
        DWORD Irq = 0xFF;

        Reg = PCIConfig_Read(Bus, Device, Function, PCI_CONFIG_INTERRUPT);
        
        // Fill in device location structure
        DevLoc.IfcType = PCIBus;
        DevLoc.BusNumber = Bus;
        DevLoc.LogicalLoc = (Bus << 16) | (Device << 8) | Function;
        DevLoc.Pin = ((PPCI_INT)(&Reg))->InterruptPin;

        if (DevLoc.Pin) {
            // Interrupts used, get IRQ from OAL
            if (!RequestIrq(&DevLoc, &Irq)) {
                DEBUGMSG(ZONE_INIT, (L"PCIBUS!PCICfgDevice: Get IRQ call failed.\r\n"));

                // No interrupts
                Irq = 0xFF;
            } else if (Irq > 254) {
                DEBUGMSG(ZONE_INIT, (L"PCIBUS!PCICfgDevice: IRQ returned from OAL is outside of range (0-254).  Ignoring.\r\n"));

                // No interrupts
                Irq = 0xFF;
            }
        }

        DEBUGMSG(ZONE_INIT, (L"RequestIrq(%d/%d/%d) returns %d\r\n", Bus, Device, Function, Irq));
        
        ((PPCI_INT)(&Reg))->InterruptLine = (BYTE)Irq;
        PCIConfig_Write(Bus, Device, Function, PCI_CONFIG_INTERRUPT, Reg);      

		// Disable expansion ROM
		PCIConfig_Write(Bus, Device, Function, PCI_CONFIG_ROM, 0);
    }

    // Set Latency register
	Info.Latency = (Info.Latency > 0) ? Info.Latency : pBusInfo->Latency;   // use global bus value if not defined for device
    if (Info.Latency) {
        // Reprogram only if non-zero
    	Reg = PCIConfig_Read(Bus, Device, Function, PCI_CONFIG_HEAD);
    	Reg = (Reg & 0xFFFF00FF) | ((Info.Latency & 0xFF) << 8);
    	PCIConfig_Write(Bus, Device, Function, PCI_CONFIG_HEAD, Reg);
    }

	// Write command value and reset device status
	if (!(pCfg->Command & (PCI_ENABLE_IO_SPACE | PCI_ENABLE_MEMORY_SPACE))) {
	    Reg = PCIConfig_Read(Bus, Device, Function, PCI_CONFIG_COMMAND_STATUS);
	    Reg &= 0x7;
	    Reg |= 0xFFFF0000 | (Info.Command & 0x000003FF);
	    PCIConfig_Write(Bus, Device, Function, PCI_CONFIG_COMMAND_STATUS, Reg);
	}
    DEBUGMSG(ZONE_FUNCTION, (L"PCIBUS!PCICfgDevice-\r\n"));
        
    return TRUE;
}


//
// Initialize and configure PCI-PCI bridge
//
static BOOL
PCICfgBridge(
    PPCI_DEV_INFO pBusInfo,
    ULONG Bus,
    ULONG Device,
    ULONG Function,
    PPCI_COMMON_CONFIG pCfg,
    PULONG pSubordinateBus,
    PULONG pMemSize,
    PULONG pIoSize,
    PULONG pPrefetchMemSize
    )
{
    ULONG BusReg;
    ULONG SecondaryMemSize;
    ULONG SecondaryIoSize;
    ULONG SecondaryPrefetchMemSize;
    ULONG i;
    ULONG Reg;

    PCI_DEV_INFO Info;

    BOOL MemPlaced = FALSE;
    BOOL IOPlaced = FALSE;
    DWORD SavedMemBase = 0xFFF00000, SavedMemSize = 0;
    DWORD SavedIOBase = 0xF000, SavedIOSize = 0;
    ULONGLONG SavedPrefetchMemBase = (ULONGLONG)0xfffffffffff00000,SavedPrefetchMemSize = 0;
    BOOL prefetchMemory=(pPrefetchMemSize!=NULL && g_PrefetchMemHead!=NULL);

    DEBUGMSG(ZONE_FUNCTION, (L"PCIBUS!PCICfgBridge+(Bus %d, Device %d, Function %d, Device ID/Vendor ID 0x%X)\r\n",
        Bus, Device, Function, PCIConfig_Read(Bus, Device, Function, 0)));
    
    // Check to see if bridge memory space already enabled
    Reg = PCIConfig_Read(Bus, Device, Function, PCI_CONFIG_COMMAND_STATUS);
    if (Reg & PCI_ENABLE_MEMORY_SPACE) {
        DWORD MemLimit;
        ULONGLONG PrefetchMemLimit ;
        
        // Memory access enabled
        MemPlaced = TRUE;

        // Save off current values of memory and I/O bases and sizes
        Reg = PCIConfig_Read(Bus, Device, Function, PCIBRIDGE_MEMORY);
        SavedMemBase = (Reg & 0xFFF0) << 16;
        MemLimit = (Reg & 0xFFF00000);

        if (MemLimit < SavedMemBase) {
            // Invalid memory base/limit pair
            SavedMemSize = 0;
        } else {
            SavedMemSize = (MemLimit + 0x000FFFFF + 1) - SavedMemBase;
        }
        Reg = PCIConfig_Read(Bus,Device,Function,PCIBRIDGE_PREFETCHABLE);
        SavedPrefetchMemBase = ((Reg<<16) & 0xfff00000);
        PrefetchMemLimit = (Reg & 0xFFF00000);
        Reg = PCIConfig_Read(Bus,Device,Function,PCIBRIDGE_BASE_UPPER32);
        SavedPrefetchMemBase += (((ULONGLONG)Reg)<<32);
        Reg = PCIConfig_Read(Bus,Device,Function,PCIBRIDGE_LIMIT_UPPER32);
        PrefetchMemLimit += (((ULONGLONG)Reg)<<32);
        if (PrefetchMemLimit<SavedPrefetchMemBase) {
            SavedPrefetchMemSize =0;
        }
        else  {
            SavedPrefetchMemSize =  (PrefetchMemLimit + 0x100000) - SavedPrefetchMemBase;
        }
        if (SavedPrefetchMemBase == 0 && PrefetchMemLimit == 0 ) {
            //Write FFFFFFFF to verify it is read only or not.
            PCIConfig_Write(Bus, Device, Function,PCIBRIDGE_PREFETCHABLE, (ULONG)-1);
            Reg = PCIConfig_Read(Bus, Device, Function, PCIBRIDGE_PREFETCHABLE);
            if ((Reg & 0xfff00000)==0) {
                prefetchMemory=FALSE;
            }
            // Recover here.
            PCIConfig_Write(Bus, Device, Function,PCIBRIDGE_PREFETCHABLE, (ULONG)0);            
        }
            
    }

    // Check to see if bridge I/O space already enabled
    Reg = PCIConfig_Read(Bus, Device, Function, PCI_CONFIG_COMMAND_STATUS);
    if (Reg & PCI_ENABLE_IO_SPACE) {
        DWORD IOLimit;
        
        // I/O access enabled
        IOPlaced = TRUE;
        
        // Save off current values of I/O base and size
        Reg = PCIConfig_Read(Bus, Device, Function, PCIBRIDGE_IO);

        SavedIOBase = (Reg & 0xF0) << 8;
        IOLimit = (Reg & 0xF000);

        if ((Reg & 0xF) == PCI_SECONDARY_IO32) {
            // 32-bit I/O
            Reg = PCIConfig_Read(Bus, Device, Function, PCIBRIDGE_IO_UPPER16);

            SavedIOBase |= (Reg & 0x0000FFFF) << 16;
            IOLimit |= (Reg & 0xFFFF0000);
        }

        if (IOLimit < SavedIOBase) {
            // Invalid I/O base/limit combination