?? os_cpu_a.asm
字號:
;
;********************************************************************************************************
; uC/OS-II
; The Real-Time Kernel
;
;
; (c) Copyright 1992-2007, Micrium, Weston, FL
; All Rights Reserved
;
; Generic ARM Port
;
; File : OS_CPU_A.ASM
; Version : V1.82
; By : Jean J. Labrosse
; Jean-Denis Hatier
;
; For : ARM7 or ARM9
; Mode : ARM or Thumb
; Toolchain : RealView Development Suite
; RealView Microcontroller Development Kit (MDK)
; ARM Developer Suite (ADS)
; Keil uVision
;********************************************************************************************************
;
;********************************************************************************************************
; PUBLIC FUNCTIONS
;********************************************************************************************************
; External references.
IMPORT OSRunning;OSRunning為1時表示建立第一個任務后啟動ucosII
IMPORT OSPrioCur;當前任務的優先級
IMPORT OSPrioHighRdy;將要運行的任務的優先級
IMPORT OSTCBCur;指向當前任務TCB的指針
IMPORT OSTCBHighRdy;指向將要運行的任務TCB的指針
IMPORT OSIntNesting;
IMPORT OSIntExit
IMPORT OSTaskSwHook;任務切換的鉤子函數
; Functions declared in this file.
EXPORT OS_CPU_SR_Save
EXPORT OS_CPU_SR_Restore
EXPORT OSStartHighRdy
EXPORT OSCtxSw
EXPORT OSIntCtxSw
; Functions related to exception handling.
EXPORT OS_CPU_ARM_ExceptResetHndlr
EXPORT OS_CPU_ARM_ExceptUndefInstrHndlr
EXPORT OS_CPU_ARM_ExceptSwiHndlr
EXPORT OS_CPU_ARM_ExceptPrefetchAbortHndlr
EXPORT OS_CPU_ARM_ExceptDataAbortHndlr
EXPORT OS_CPU_ARM_ExceptAddrAbortHndlr
EXPORT OS_CPU_ARM_ExceptIrqHndlr
EXPORT OS_CPU_ARM_ExceptFiqHndlr
IMPORT OS_CPU_ExceptHndlr
;********************************************************************************************************
; EQUATES
;********************************************************************************************************
OS_CPU_ARM_CONTROL_INT_DIS EQU 0xC0 ; Disable both FIQ and IRQ.
OS_CPU_ARM_CONTROL_FIQ_DIS EQU 0x40 ; Disable FIQ.
OS_CPU_ARM_CONTROL_IRQ_DIS EQU 0x80 ; Disable IRQ.
OS_CPU_ARM_CONTROL_THUMB EQU 0x20 ; Set THUMB mode.
OS_CPU_ARM_CONTROL_ARM EQU 0x00 ; Set ARM mode.
OS_CPU_ARM_MODE_MASK EQU 0x1F
OS_CPU_ARM_MODE_USR EQU 0x10
OS_CPU_ARM_MODE_FIQ EQU 0x11
OS_CPU_ARM_MODE_IRQ EQU 0x12
OS_CPU_ARM_MODE_SVC EQU 0x13
OS_CPU_ARM_MODE_ABT EQU 0x17
OS_CPU_ARM_MODE_UND EQU 0x1B
OS_CPU_ARM_MODE_SYS EQU 0x1F
OS_CPU_ARM_EXCEPT_RESET EQU 0x00
OS_CPU_ARM_EXCEPT_UNDEF_INSTR EQU 0x01
OS_CPU_ARM_EXCEPT_SWI EQU 0x02
OS_CPU_ARM_EXCEPT_PREFETCH_ABORT EQU 0x03
OS_CPU_ARM_EXCEPT_DATA_ABORT EQU 0x04
OS_CPU_ARM_EXCEPT_ADDR_ABORT EQU 0x05
OS_CPU_ARM_EXCEPT_IRQ EQU 0x06
OS_CPU_ARM_EXCEPT_FIQ EQU 0x07
;********************************************************************************************************
; CODE GENERATION DIRECTIVES
;********************************************************************************************************
REQUIRE8
PRESERVE8
;*********************************************************************************************************
; CRITICAL SECTION METHOD 3 FUNCTIONS
;
; Description: Disable/Enable interrupts by preserving the state of interrupts. Generally speaking you
; would store the state of the interrupt disable flag in the local variable 'cpu_sr' and then
; disable interrupts. 'cpu_sr' is allocated in all of uC/OS-II's functions that need to
; disable interrupts. You would restore the interrupt disable state by copying back 'cpu_sr'
; into the CPU's status register.
;
; Prototypes : OS_CPU_SR OS_CPU_SR_Save (void);
; void OS_CPU_SR_Restore (OS_CPU_SR os_cpu_sr);
;
;
; Note(s) : (1) These functions are used in general like this:
;
; void Task (void *p_arg)
; {
; /* Allocate storage for CPU status register. */
; #if (OS_CRITICAL_METHOD == 3)
; OS_CPU_SR os_cpu_sr;
; #endif
;
; :
; :
; OS_ENTER_CRITICAL(); /* os_cpu_sr = OS_CPU_SR_Save(); */
; :
; :
; OS_EXIT_CRITICAL(); /* OS_CPU_SR_Restore(cpu_sr); */
; :
; :
; }
;*********************************************************************************************************
AREA CODE, CODE, READONLY
CODE32
OS_CPU_SR_Save
MRS R0, CPSR
ORR R1, R0, #OS_CPU_ARM_CONTROL_INT_DIS ; Set IRQ and FIQ bits in CPSR to disable all interrupts.
MSR CPSR_c, R1
BX LR ; Disabled, return the original CPSR contents in R0.
OS_CPU_SR_Restore
MSR CPSR_c, R0
BX LR
;*********************************************************************************************************
; START MULTITASKING
; void OSStartHighRdy(void)
;
; Note(s) : 1) OSStartHighRdy() MUST:
; a) Call OSTaskSwHook() then,
; b) Set OSRunning to TRUE,
; c) Switch to the highest priority task.
;*********************************************************************************************************
AREA CODE, CODE, READONLY
CODE32
OSStartHighRdy
; Change to SVC mode.
MSR CPSR_c, #(OS_CPU_ARM_CONTROL_INT_DIS | OS_CPU_ARM_MODE_SVC)
LDR R0, __OS_TaskSwHook ; OSTaskSwHook();
MOV LR, PC
BX R0
LDR R0, __OS_Running ; OSRunning = TRUE;
MOV R1, #1
STRB R1, [R0]
; SWITCH TO HIGHEST PRIORITY TASK:
LDR R0, __OS_TCBHighRdy ; Get highest priority task TCB address,
LDR R0, [R0] ; Get stack pointer,
LDR SP, [R0] ; Switch to the new stack,
LDR R0, [SP], #4 ; Pop new task's CPSR,
MSR SPSR_cxsf, R0
LDMFD SP!, {R0-R12, LR, PC}^ ; Pop new task's context.
;*********************************************************************************************************
; PERFORM A CONTEXT SWITCH (From task level) - OSCtxSw()
;
; Note(s) : 1) OSCtxSw() is called in SVC mode with BOTH FIQ and IRQ interrupts DISABLED.
;
; 2) The pseudo-code for OSCtxSw() is:
; a) Save the current task's context onto the current task's stack,
; b) OSTCBCur->OSTCBStkPtr = SP;
; c) OSTaskSwHook();
; d) OSPrioCur = OSPrioHighRdy;
; e) OSTCBCur = OSTCBHighRdy;
; f) SP = OSTCBHighRdy->OSTCBStkPtr;
; g) Restore the new task's context from the new task's stack,
; h) Return to new task's code.
;
; 3) Upon entry:
; OSTCBCur points to the OS_TCB of the task to suspend,
; OSTCBHighRdy points to the OS_TCB of the task to resume.
;*********************************************************************************************************
AREA CODE, CODE, READONLY
CODE32
OSCtxSw
; SAVE CURRENT TASK'S CONTEXT:
STMFD SP!, {LR} ; Push return address,
STMFD SP!, {LR}
STMFD SP!, {R0-R12} ; Push registers,
MRS R0, CPSR ; Push current CPSR,
TST LR, #1 ; See if called from Thumb mode,
ORRNE R0, R0, #OS_CPU_ARM_CONTROL_THUMB ; If yes, set the T-bit.
STMFD SP!, {R0}
LDR R0, __OS_TCBCur ; OSTCBCur->OSTCBStkPtr = SP;
LDR R1, [R0]
STR SP, [R1]
LDR R0, __OS_TaskSwHook ; OSTaskSwHook();
MOV LR, PC
BX R0
LDR R0, __OS_PrioCur ; OSPrioCur = OSPrioHighRdy;
LDR R1, __OS_PrioHighRdy
LDRB R2, [R1]
STRB R2, [R0]
LDR R0, __OS_TCBCur ; OSTCBCur = OSTCBHighRdy;
LDR R1, __OS_TCBHighRdy
LDR R2, [R1]
STR R2, [R0]
LDR SP, [R2] ; SP = OSTCBHighRdy->OSTCBStkPtr;
; RESTORE NEW TASK'S CONTEXT:
LDMFD SP!, {R0} ; Pop new task's CPSR,
MSR SPSR_cxsf, R0
LDMFD SP!, {R0-R12, LR, PC}^ ; Pop new task's context.
;*********************************************************************************************************
; PERFORM A CONTEXT SWITCH (From interrupt level) - OSIntCtxSw()
;
; Note(s) : 1) OSIntCtxSw() is called in SVC mode with BOTH FIQ and IRQ interrupts DISABLED.
;
; 2) The pseudo-code for OSCtxSw() is:
; a) OSTaskSwHook();
; b) OSPrioCur = OSPrioHighRdy;
; c) OSTCBCur = OSTCBHighRdy;
; d) SP = OSTCBHighRdy->OSTCBStkPtr;
; e) Restore the new task's context from the new task's stack,
; f) Return to new task's code.
;
; 3) Upon entry:
; OSTCBCur points to the OS_TCB of the task to suspend,
; OSTCBHighRdy points to the OS_TCB of the task to resume.
;*********************************************************************************************************
AREA CODE, CODE, READONLY
CODE32
OSIntCtxSw
LDR R0, __OS_TaskSwHook ; OSTaskSwHook();
MOV LR, PC
BX R0
LDR R0, __OS_PrioCur ; OSPrioCur = OSPrioHighRdy;
LDR R1, __OS_PrioHighRdy
LDRB R2, [R1]
STRB R2, [R0]
LDR R0, __OS_TCBCur ; OSTCBCur = OSTCBHighRdy;
LDR R1, __OS_TCBHighRdy
LDR R2, [R1]
STR R2, [R0]
LDR SP, [R2] ; SP = OSTCBHighRdy->OSTCBStkPtr;
; RESTORE NEW TASK'S CONTEXT:
LDMFD SP!, {R0} ; Pop new task's CPSR,
MSR SPSR_cxsf, R0
LDMFD SP!, {R0-R12, LR, PC}^ ; Pop new task's context.
;********************************************************************************************************
; RESET EXCEPTION HANDLER
;
; Register Usage: R0 Exception Type
; R1
; R2
; R3 Return PC
;********************************************************************************************************
AREA CODE, CODE, READONLY
CODE32
OS_CPU_ARM_ExceptResetHndlr
; LR offset to return from this exception: 0.
; (there is no way to return from a RESET exception).
STMFD SP!, {R0-R12, LR} ; Push working registers.
MOV R3, LR ; Save link register.
MOV R0, #OS_CPU_ARM_EXCEPT_RESET ; Set exception ID to OS_CPU_ARM_EXCEPT_RESET.
B OS_CPU_ARM_ExceptHndlr ; Branch to global exception handler.
;********************************************************************************************************
; UNDEFINED INSTRUCTION EXCEPTION HANDLER
;
; Register Usage: R0 Exception Type
; R1
; R2
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