"Watchdog timer test", "watchdog", \		"  This test checks the watchdog timer.", \		POST_RAM | POST_POWERON | POST_REBOOT, \		&watchdog_post_test \	}......int watchdog_post_test(bd_t *bd, int flags){	unsigned long start_time;	if (flags & POST_REBOOT) {		/* Test passed */		return 0;	} else {		/* disable interrupts */		disable_interrupts();		/* 10-second delay */		...		/* if we've reached this, the watchdog timer does not work */		enable_interrupts();		return 1;	}}...2.2. Hardware-specific detailsThis project will also develop a set of POST tests for MPC8xx- basedsystems. This section provides technical details of how it will bedone.2.2.1. Generic PPC testsThe following generic POST tests will be developed:  o) CPU test     This test will check the arithmetic logic unit (ALU) of CPU. The     test will take several milliseconds and will run on normal     booting.  o) Cache test     This test will verify the CPU cache (L1 cache). The test will     run on normal booting.  o) Memory test     This test will examine RAM and check it for errors. The test     will always run on booting. On normal booting, only a limited     amount of RAM will be checked. On power-fail booting a fool     memory check-up will be performed.2.2.1.1. CPU testThis test will verify the following ALU instructions:  o) Condition register istructions     This group will contain: mtcrf, mfcr, mcrxr, crand, crandc,     cror, crorc, crxor, crnand, crnor, creqv, mcrf.     The mtcrf/mfcr instructions will be tested by loading different     values into the condition register (mtcrf), moving its value to     a general-purpose register (mfcr) and comparing this value with     the expected one. The mcrxr instruction will be tested by     loading a fixed value into the XER register (mtspr), moving XER     value to the condition register (mcrxr), moving it to a     general-purpose register (mfcr) and comparing the value of this     register with the expected one. The rest of instructions will be     tested by loading a fixed value into the condition register     (mtcrf), executing each instruction several times to modify all     4-bit condition fields, moving the value of the conditional     register to a general-purpose register (mfcr) and comparing it     with the expected one.  o) Integer compare instructions     This group will contain: cmp, cmpi, cmpl, cmpli.     To verify these instructions the test will run them with     different combinations of operands, read the condition register     value and compare it with the expected one. More specifically,     the test will contain a pre-built table containing the     description of each test case: the instruction, the values of     the operands, the condition field to save the result in and the     expected result.  o) Arithmetic instructions     This group will contain: add, addc, adde, addme, addze, subf,     subfc, subfe, subme, subze, mullw, mulhw, mulhwu, divw, divwu,     extsb, extsh.     The test will contain a pre-built table of instructions,     operands, expected results and expected states of the condition     register. For each table entry, the test will cyclically use     different sets of operand registers and result registers. For     example, for instructions that use 3 registers on the first     iteration r0/r1 will be used as operands and r2 for result. On     the second iteration, r1/r2 will be used as operands and r3 as     for result and so on. This will enable to verify all     general-purpose registers.  o) Logic instructions     This group will contain: and, andc, andi, andis, or, orc, ori,     oris, xor, xori, xoris, nand, nor, neg, eqv, cntlzw.     The test scheme will be identical to that from the previous     point.  o) Shift instructions     This group will contain: slw, srw, sraw, srawi, rlwinm, rlwnm,     rlwimi     The test scheme will be identical to that from the previous     point.  o) Branch instructions     This group will contain: b, bl, bc.     The first 2 instructions (b, bl) will be verified by jumping to     a fixed address and checking whether control was transfered to     that very point. For the bl instruction the value of the link     register will be checked as well (using mfspr). To verify the bc     instruction various combinations of the BI/BO fields, the CTR     and the condition register values will be checked. The list of     such combinations will be pre-built and linked in U-Boot at     build time.  o) Load/store instructions     This group will contain: lbz(x)(u), lhz(x)(u), lha(x)(u),     lwz(x)(u), stb(x)(u), sth(x)(u), stw(x)(u).     All operations will be performed on a 16-byte array. The array     will be 4-byte aligned. The base register will point to offset     8. The immediate offset (index register) will range in [-8 ...     +7]. The test cases will be composed so that they will not cause     alignment exceptions. The test will contain a pre-built table     describing all test cases. For store instructions, the table     entry will contain: the instruction opcode, the value of the     index register and the value of the source register. After     executing the instruction, the test will verify the contents of     the array and the value of the base register (it must change for     "store with update" instructions). For load instructions, the     table entry will contain: the instruction opcode, the array     contents, the value of the index register and the expected value     of the destination register. After executing the instruction,     the test will verify the value of the destination register and     the value of the base register (it must change for "load with     update" instructions).  o) Load/store multiple/string instructionsThe CPU test will run in RAM in order to allow run-time modificationof the code to reduce the memory footprint.2.2.1.2 Special-Purpose Registers TestsTBD.2.2.1.3. Cache testTo verify the data cache operation the following test scenarios willbe used:  1) Basic test #1    - turn on the data cache    - switch the data cache to write-back or write-through mode    - invalidate the data cache    - write the negative pattern to a cached area    - read the area    The negative pattern must be read at the last step  2) Basic test #2    - turn on the data cache    - switch the data cache to write-back or write-through mode    - invalidate the data cache    - write the zero pattern to a cached area    - turn off the data cache    - write the negative pattern to the area    - turn on the data cache    - read the area    The negative pattern must be read at the last step  3) Write-through mode test    - turn on the data cache    - switch the data cache to write-through mode    - invalidate the data cache    - write the zero pattern to a cached area    - flush the data cache    - write the negative pattern to the area    - turn off the data cache    - read the area    The negative pattern must be read at the last step  4) Write-back mode test    - turn on the data cache    - switch the data cache to write-back mode    - invalidate the data cache    - write the negative pattern to a cached area    - flush the data cache    - write the zero pattern to the area    - invalidate the data cache    - read the area    The negative pattern must be read at the last stepTo verify the instruction cache operation the following testscenarios will be used:  1) Basic test #1    - turn on the instruction cache    - unlock the entire instruction cache    - invalidate the instruction cache    - lock a branch instruction in the instruction cache    - replace the branch instruction with "nop"    - jump to the branch instruction    - check that the branch instruction was executed  2) Basic test #2    - turn on the instruction cache    - unlock the entire instruction cache    - invalidate the instruction cache    - jump to a branch instruction    - check that the branch instruction was executed    - replace the branch instruction with "nop"    - invalidate the instruction cache    - jump to the branch instruction    - check that the "nop" instruction was executedThe CPU test will run in RAM in order to allow run-time modificationof the code.2.2.1.4. Memory testThe memory test will verify RAM using sequential writes and readsto/from RAM. Specifically, there will be several test cases that willuse different patterns to verify RAM. Each test case will first filla region of RAM with one pattern and then read the region back andcompare its contents with the pattern. The following patterns will beused: 1) zero pattern (0x00000000) 2) negative pattern (0xffffffff) 3) checkerboard pattern (0x55555555, 0xaaaaaaaa) 4) bit-flip pattern ((1 << (offset % 32)), ~(1 << (offset % 32))) 5) address pattern (offset, ~offset)Patterns #1, #2 will help to find unstable bits. Patterns #3, #4 willbe used to detect adherent bits, i.e. bits whose state may randomlychange if adjacent bits are modified. The last pattern will be usedto detect far-located errors, i.e. situations when writing to onelocation modifies an area located far from it. Also, usage of thelast pattern will help to detect memory controller misconfigurationswhen RAM represents a cyclically repeated portion of a smaller size.Being run in normal mode, the test will verify only small 4Kb regionsof RAM around each 1Mb boundary. For example, for 64Mb RAM thefollowing areas will be verified: 0x00000000-0x00000800,0x000ff800-0x00100800, 0x001ff800-0x00200800, ..., 0x03fff800-0x04000000. If the test is run in power-fail mode, it will verify thewhole RAM.The memory test will run in ROM before relocating U-Boot to RAM inorder to allow RAM modification without saving its contents.2.2.2. Common testsThis section describes tests that are not based on any hardwarepeculiarities and use common U-Boot interfaces only. These tests donot need any modifications for porting them to another board/CPU.2.2.2.1. I2C testFor verifying the I2C bus, a full I2C bus scanning will be performedusing the i2c_probe() routine. If any I2C device is found, the testwill be considered as passed, otherwise failed. This particular waywill be used because it provides the most common method of testing.For example, using the internal loopback mode of the CPM I2Ccontroller for testing would not work on boards where the softwareI2C driver (also known as bit-banged driver) is used.2.2.2.2. Watchdog timer testTo test the watchdog timer the scheme mentioned above (refer tosection "Hazardous tests") will be used. Namely, this test will bemarked with the POST_REBOOT bit flag. On the first iteration, thetest routine will make a 10-second delay. If the system does notreboot during this delay, the watchdog timer is not operational andthe test fails. If the system reboots, on the second iteration thePOST_REBOOT bit will be set in the flag argument to the test routine.The test routine will check this bit and report a success if it isset.2.2.2.3. RTC testThe RTC test will use the rtc_get()/rtc_set() routines. The followingfeatures will be verified:  o) Time uniformity     This will be verified by reading RTC in polling within a short     period of time (5-10 seconds).  o) Passing month boundaries     This will be checked by setting RTC to a second before a month     boundary and reading it after its passing the boundary. The test     will be performed for both leap- and nonleap-years.2.2.3. MPC8xx peripherals testsThis project will develop a set of tests verifying the peripheralunits of MPC8xx processors. Namely, the following controllers of theMPC8xx communication processor module (CPM) will be tested:  o) Serial Management Controllers (SMC)  o) Serial Communication Controllers (SCC)2.2.3.1. Ethernet tests (SCC)The internal (local) loopback mode will be used to test SCC. To dothat the controllers will be configured accordingly and severalpackets will be transmitted. These tests may be enhanced in future touse external loopback for testing. That will need appropriatereconfiguration of the physical interface chip.The test routines for the SCC ethernet tests will be located incpu/mpc8xx/scc.c.2.2.3.2. UART tests (SMC/SCC)To perform these tests the internal (local) loopback mode will beused. The SMC/SCC controllers will be configured to connect thetransmitter output to the receiver input. After that, several byteswill be transmitted. These tests may be enhanced to make to perform"external" loopback test using a loopback cable. In this case, thetest will be executed manually.The test routine for the SMC/SCC UART tests will be located incpu/mpc8xx/serial.c.2.2.3.3. USB testTBD2.2.3.4. SPI testTBD