.global _InitC5402 
	.global _OpenMcBSP
	.global _CloseMcBSP 
	.global _READAD50 
	.global _WRITEAD50
	.include MMRegs.h
_InitC5402:
	NOP
	LD #0, DP ; reset data–page pointer
	STM #0, CLKMD ; software setting of DSP clock
	STM #0, CLKMD ; (to divider mode before setting)
TstStatu1:
    LDM CLKMD, A
    AND #01b, A ;poll STATUS bit
    BC TstStatu1, ANEQ	
	STM #0xF7FF, CLKMD ; set C5402 DSP clock to 10MHz	
* STM #0x4007, CLKMD ; set C5402 DSP clock to 100MHz
; (based on DSK crystal at 20MHz)
******* Configure C5402 System Registers *******
	STM #0x7fff, SWWSR ; 2 wait cycle for IO space &
; 0 wait cycle for data&prog spaces
	STM #0x0000,BSCR ; set wait states for bank switch:
; 64k mem bank, extra 0 cycle between
; consecutive prog/data read
;	STM #0x1800,ST0 ; ST0 at default setting
;	STM #0x2900,ST1 ; ST1 at default setting(note:INTX=1)
;	STM #0x00A0,PMST ; MC mode & OVLY=1, vectors at 0080h
******* Set up Timer Control Registers *******
	STM #0x0010, TCR ; stop on–chip timer0
	STM #0x0010, TCR1 ; stop on–chip timer1
; Timer0 is used as main loop timer
;	STM #2499, PRD ; timer0 rate=CPUCLK/1/(PRD+1)
; =40M/2500=16KHz
* STM #6249, PRD ; if CPU at 100M/6250=16KHz  


	
******* Initialize McBSP1 Registers *******
	STM SPCR1, McBSP1_SPSA ; register subaddr of SPCR1
	STM #0000h, McBSP1_SPSD ; McBSP1 recv = left–justify
; RINT generated by frame sync
	STM SPCR2, McBSP1_SPSA ; register subaddr for SPCR2
; XINT generated by frame sync
	STM #0000h, McBSP1_SPSD ; McBSP1 Tx = FREE(clock stops
; to run after SW breakpoint
	STM RCR1, McBSP1_SPSA ; register subaddr of RCR1
	STM #0040h, McBSP1_SPSD ; recv frame1 Dlength = 16 bits
	STM RCR2, McBSP1_SPSA ; register subaddr of RCR2 
	STM #0040h, McBSP1_SPSD ; recv Phase = 1
; ret frame2 Dlength = 16bits
	STM XCR1, McBSP1_SPSA ; register subaddr of XCR1
	STM #0040h, McBSP1_SPSD ; set the same as recv
	STM XCR2, McBSP1_SPSA ; register subaddr of XCR2
	STM #0040h, McBSP1_SPSD ; set the same as recv
	STM PCR, McBSP1_SPSA ; register subaddress of PCR
	STM #000eh, McBSP1_SPSD ; clk and frame from external (slave)
; FS at pulse–mode(00)
******* Finish DSP Initialization *******
	STM #0x0000, IMR ; disable peripheral interrupts
	STM #0xFFFF, IFR ; clear the intrupts’ flags
	RET ; return to main
	NOP
	NOP 
	
******* Waiting for McBSP0 RX Finished *******
IfRxRDY1:
	NOP
	STM SPCR1, McBSP1_SPSA ; enable McBSP1 Rx
	LDM McBSP1_SPSD, A
	AND #0002h, A ; mask RRDY bit
	BC IfRxRDY1, AEQ ; keep checking
	NOP
	NOP
	RET ; return
	NOP
	NOP
******* Waiting for McBSP0 TX Finished *******
IfTxRDY1:
	NOP
	STM SPCR2, McBSP1_SPSA ; enable McBSP1 Tx
	LDM McBSP1_SPSD, A
	AND #0002h, A ; mask TRDY bit
	BC IfTxRDY1, AEQ ; keep checking 
	NOP
	NOP
	RET ; return
	NOP
	NOP

******************************************
******************************************
_OpenMcBSP:

	stm    1000h,ar0
    st     00,*ar0
	portw *ar0,8001h   ;reset AD50  XF=0
	NOP
	call wait
	NOP
	NOP
	NOP
	STM SPCR1, McBSP1_SPSA ; enable McBSP1 RX for ADC data in
	LDM McBSP1_SPSD,A
	OR #0x0001, A
	STLM A, McBSP1_SPSD
	STM SPCR2, McBSP1_SPSA ; enable McBSP1 TX for DTMF out
	LDM McBSP1_SPSD,A
	OR #0x0001, A
	STLM A, McBSP1_SPSD
	LD #0h, DP ; load data page 0
	rpt #23
	NOP  
	stm  1000h,ar0
	st    0xff,*ar0
	portw  *ar0,8001h ;out reset aD50 XF=1
	NOP
	NOP
	;STM 0x4007,CLKMD
	
	
;	CALL IfTxRDY1
;	STM #0x0101, McBSP1_DXR1
	
;	CALL IfTxRDY1
;	STM #0x0208, McBSP1_DXR1

;;	rsbx	xf
;;  NOP
;;NOP       
    CALL IfTxRDY1
	STM #0x0001, McBSP1_DXR1;request secondary communication
	NOP
	CALL IfTxRDY1 
	STM #0100h, McBSP1_DXR1;write 00h to register 1

	CALL IfTxRDY1
	STM #0000h, McBSP1_DXR1 
	
	NOP
	NOP
	rpt #20h
	nop
           
	CALL IfTxRDY1
	STM #0x0001, McBSP1_DXR1;request secondary communication
	CALL IfTxRDY1 
	STM #0200h, McBSP1_DXR1;write 00h to register 2 
	
	CALL IfTxRDY1
	STM #0000h, McBSP1_DXR1 	
			    
   	CALL IfTxRDY1
	STM #0x0001, McBSP1_DXR1;request secondary communication
	CALL IfTxRDY1 
	STM #0300h, McBSP1_DXR1;write 00h to register 3

	CALL IfTxRDY1
	STM #0000h, McBSP1_DXR1 

    CALL IfTxRDY1
	STM #0x0001, McBSP1_DXR1;request secondary communication
	CALL IfTxRDY1 
	STM #0490h, McBSP1_DXR1;write 00h to register 4
							;bypass internal DPLL
							;and select the Sample Frequency  

	CALL IfTxRDY1
	STM #0000h, McBSP1_DXR1 
	
;	CALL IfTxRDY1
;	STM #0x0001, McBSP1_DXR1
;	CALL IfTxRDY1
;	STM #0102h, McBSP1_DXR1 ;enable digital loopback 	
		
;	CALL IfTxRDY1
;	STM #0x0001, McBSP1_DXR1
;	CALL IfTxRDY1
;	STM #0208h, McBSP1_DXR1 ;enable analog loopback

	RET
	NOP
	NOP

 
*********************
_CloseMcBSP:
	STM SPCR1, McBSP1_SPSA ; disable McBSP0 RX
	LDM McBSP1_SPSD,A
	AND #0xFFFE, A
	STLM A, McBSP1_SPSD
	STM SPCR2, McBSP1_SPSA ; disable McBSP0 TX
	LDM McBSP1_SPSD,A
	AND #0xFFFE, A
	STLM A, McBSP1_SPSD
	RPT #5
	RET
	NOP
	NOP



_READAD50:
	stm		0x00ff,ar3
	stm		0x3000,ar2
	
loopa:
	CALL IfRxRDY1
	ldm	  McBSP1_DRR1,b
	stl	  b,*ar2+
;    banz  loopa,*ar3- 
    
	nop
	nop 
	ret
	nop
	nop
	
_WRITEAD50:
	stm		0x0001,ar3
	stm		0x2b00,ar2
loopb:
	CALL 	IfTxRDY1   
	ldu		*ar2+,B
	and     #0fffeh,b ;mask the LSB
	stlm    B, McBSP1_DXR1
;	banz	loopb,*ar3-
	nop
	nop
	ret
	nop
	nop 
	
wait: 
	stm 	20h,ar3
loop1:              
	stm 	020h,ar4
loop2:
	banz 	loop2,*ar4-
	banz 	loop1,*ar3-
	ret     
	nop
	nop
	nop
	nop
	
	.end
************************************************************************
** End of File –– InitC5402.asm
************************************************************************