{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jun 19 11:06:03 2008 " "Info: Processing started: Thu Jun 19 11:06:03 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off test_div -c test_div " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off test_div -c test_div" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "test_div.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file test_div.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 test_div " "Info: Found entity 1: test_div" {  } { { "test_div.bdf" "" { Schematic "E:/TMP/fpga_div/test_div.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "test_div " "Info: Elaborating entity \"test_div\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "divide0.vhd 2 1 " "Warning: Using design file divide0.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 divide0-SYN " "Info: Found design unit 1: divide0-SYN" {  } { { "divide0.vhd" "" { Text "E:/TMP/fpga_div/divide0.vhd" 50 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 divide0 " "Info: Found entity 1: divide0" {  } { { "divide0.vhd" "" { Text "E:/TMP/fpga_div/divide0.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "divide0 divide0:inst " "Info: Elaborating entity \"divide0\" for hierarchy \"divide0:inst\"" {  } { { "test_div.bdf" "inst" { Schematic "E:/TMP/fpga_div/test_div.bdf" { { 392 352 536 488 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus60/libraries/megafunctions/lpm_divide.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus60/libraries/megafunctions/lpm_divide.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide " "Info: Found entity 1: lpm_divide" {  } { { "lpm_divide.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/lpm_divide.tdf" 116 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_divide divide0:inst\|lpm_divide:lpm_divide_component " "Info: Elaborating entity \"lpm_divide\" for hierarchy \"divide0:inst\|lpm_divide:lpm_divide_component\"" {  } { { "divide0.vhd" "lpm_divide_component" { Text "E:/TMP/fpga_div/divide0.vhd" 78 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "divide0:inst\|lpm_divide:lpm_divide_component " "Info: Elaborated megafunction instantiation \"divide0:inst\|lpm_divide:lpm_divide_component\"" {  } { { "divide0.vhd" "" { Text "E:/TMP/fpga_div/divide0.vhd" 78 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_q8p.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_q8p.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_q8p " "Info: Found entity 1: lpm_divide_q8p" {  } { { "db/lpm_divide_q8p.tdf" "" { Text "E:/TMP/fpga_div/db/lpm_divide_q8p.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_divide_q8p divide0:inst\|lpm_divide:lpm_divide_component\|lpm_divide_q8p:auto_generated " "Info: Elaborating entity \"lpm_divide_q8p\" for hierarchy \"divide0:inst\|lpm_divide:lpm_divide_component\|lpm_divide_q8p:auto_generated\"" {  } { { "lpm_divide.tdf" "auto_generated" { Text "d:/altera/quartus60/libraries/megafunctions/lpm_divide.tdf" 145 9 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_79h.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_79h.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_79h " "Info: Found entity 1: sign_div_unsign_79h" {  } { { "db/sign_div_unsign_79h.tdf" "" { Text "E:/TMP/fpga_div/db/sign_div_unsign_79h.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sign_div_unsign_79h divide0:inst\|lpm_divide:lpm_divide_component\|lpm_divide_q8p:auto_generated\|sign_div_unsign_79h:divider " "Info: Elaborating entity \"sign_div_unsign_79h\" for hierarchy \"divide0:inst\|lpm_divide:lpm_divide_component\|lpm_divide_q8p:auto_generated\|sign_div_unsign_79h:divider\"" {  } { { "db/lpm_divide_q8p.tdf" "divider" { Text "E:/TMP/fpga_div/db/lpm_divide_q8p.tdf" 32 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_aue.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_aue.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_aue " "Info: Found entity 1: alt_u_div_aue" {  } { { "db/alt_u_div_aue.tdf" "" { Text "E:/TMP/fpga_div/db/alt_u_div_aue.tdf" 54 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_u_div_aue divide0:inst\|lpm_divide:lpm_divide_component\|lpm_divide_q8p:auto_generated\|sign_div_unsign_79h:divider\|alt_u_div_aue:divider " "Info: Elaborating entity \"alt_u_div_aue\" for hierarchy \"divide0:inst\|lpm_divide:lpm_divide_component\|lpm_divide_q8p:auto_generated\|sign_div_unsign_79h:divider\|alt_u_div_aue:divider\"" {  } { { "db/sign_div_unsign_79h.tdf" "divider" { Text "E:/TMP/fpga_div/db/sign_div_unsign_79h.tdf" 36 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_3dc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_3dc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_3dc " "Info: Found entity 1: add_sub_3dc" {  } { { "db/add_sub_3dc.tdf" "" { Text "E:/TMP/fpga_div/db/add_sub_3dc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_3dc divide0:inst\|lpm_divide:lpm_divide_component\|lpm_divide_q8p:auto_generated\|sign_div_unsign_79h:divider\|alt_u_div_aue:divider\|add_sub_3dc:add_sub_0 " "Info: Elaborating entity \"add_sub_3dc\" for hierarchy \"divide0:inst\|lpm_divide:lpm_divide_component\|lpm_divide_q8p:auto_generated\|sign_div_unsign_79h:divider\|alt_u_div_aue:divider\|add_sub_3dc:add_sub_0\"" {  } { { "db/alt_u_div_aue.tdf" "add_sub_0" { Text "E:/TMP/fpga_div/db/alt_u_div_aue.tdf" 63 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_4dc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_4dc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_4dc " "Info: Found entity 1: add_sub_4dc" {  } { { "db/add_sub_4dc.tdf" "" { Text "E:/TMP/fpga_div/db/add_sub_4dc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_4dc divide0:inst\|lpm_divide:lpm_divide_component\|lpm_divide_q8p:auto_generated\|sign_div_unsign_79h:divider\|alt_u_div_aue:divider\|add_sub_4dc:add_sub_1 " "Info: Elaborating entity \"add_sub_4dc\" for hierarchy \"divide0:inst\|lpm_divide:lpm_divide_component\|lpm_divide_q8p:auto_generated\|sign_div_unsign_79h:divider\|alt_u_div_aue:divider\|add_sub_4dc:add_sub_1\"" {  } { { "db/alt_u_div_aue.tdf" "add_sub_1" { Text "E:/TMP/fpga_div/db/alt_u_div_aue.tdf" 64 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_kec.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_kec.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_kec " "Info: Found entity 1: add_sub_kec" {  } { { "db/add_sub_kec.tdf" "" { Text "E:/TMP/fpga_div/db/add_sub_kec.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_kec divide0:inst\|lpm_divide:lpm_divide_component\|lpm_divide_q8p:auto_generated\|sign_div_unsign_79h:divider\|alt_u_div_aue:divider\|add_sub_kec:add_sub_10 " "Info: Elaborating entity \"add_sub_kec\" for hierarchy \"divide0:inst\|lpm_divide:lpm_divide_component\|lpm_divide_q8p:auto_generated\|sign_div_unsign_79h:divider\|alt_u_div_aue:divider\|add_sub_kec:add_sub_10\"" {  } { { "db/alt_u_div_aue.tdf" "add_sub_10" { Text "E:/TMP/fpga_div/db/alt_u_div_aue.tdf" 65 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_lec.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_lec.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_lec " "Info: Found entity 1: add_sub_lec" {  } { { "db/add_sub_lec.tdf" "" { Text "E:/TMP/fpga_div/db/add_sub_lec.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_lec divide0:inst\|lpm_divide:lpm_divide_component\|lpm_divide_q8p:auto_generated\|sign_div_unsign_79h:divider\|alt_u_div_aue:divider\|add_sub_lec:add_sub_11 " "Info: Elaborating entity \"add_sub_lec\" for hierarchy \"divide0:inst\|lpm_divide:lpm_divide_component\|lpm_divide_q8p:auto_generated\|sign_div_unsign_79h:divider\|alt_u_div_aue:divider\|add_sub_lec:add_sub_11\"" {  } { { "db/alt_u_div_aue.tdf" "add_sub_11" { Text "E:/TMP/fpga_div/db/alt_u_div_aue.tdf" 66 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_mec.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_mec.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_mec " "Info: Found entity 1: add_sub_mec" {  } { { "db/add_sub_mec.tdf" "" { Text "E:/TMP/fpga_div/db/add_sub_mec.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_mec divide0:inst\|lpm_divide:lpm_divide_component\|lpm_divide_q8p:auto_generated\|sign_div_unsign_79h:divider\|alt_u_div_aue:divider\|add_sub_mec:add_sub_12 " "Info: Elaborating entity \"add_sub_mec\" for hierarchy \"divide0:inst\|lpm_divide:lpm_divide_component\|lpm_divide_q8p:auto_generated\|sign_div_unsign_79h:divider\|alt_u_div_aue:divider\|add_sub_mec:add_sub_12\"" {  } { { "db/alt_u_div_aue.tdf" "add_sub_12" { Text "E:/TMP/fpga_div/db/alt_u_div_aue.tdf" 67 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_nec.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_nec.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_nec " "Info: Found entity 1: add_sub_nec" {  } { { "db/add_sub_nec.tdf" "" { Text "E:/TMP/fpga_div/db/add_sub_nec.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_nec divide0:inst\|lpm_divide:lpm_divide_component\|lpm_divide_q8p:auto_generated\|sign_div_unsign_79h:divider\|alt_u_div_aue:divider\|add_sub_nec:add_sub_13 " "Info: Elaborating entity \"add_sub_nec\" for hierarchy \"divide0:inst\|lpm_divide:lpm_divide_component\|lpm_divide_q8p:auto_generated\|sign_div_unsign_79h:divider\|alt_u_div_aue:divider\|add_sub_nec:add_sub_13\"" {  } { { "db/alt_u_div_aue.tdf" "add_sub_13" { Text "E:/TMP/fpga_div/db/alt_u_div_aue.tdf" 68 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_oec.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_oec.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_oec " "Info: Found entity 1: add_sub_oec" {  } { { "db/add_sub_oec.tdf" "" { Text "E:/TMP/fpga_div/db/add_sub_oec.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}