{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_oec divide0:inst\|lpm_divide:lpm_divide_component\|lpm_divide_q8p:auto_generated\|sign_div_unsign_79h:divider\|alt_u_div_aue:divider\|add_sub_oec:add_sub_14 " "Info: Elaborating entity \"add_sub_oec\" for hierarchy \"divide0:inst\|lpm_divide:lpm_divide_component\|lpm_divide_q8p:auto_generated\|sign_div_unsign_79h:divider\|alt_u_div_aue:divider\|add_sub_oec:add_sub_14\"" {  } { { "db/alt_u_div_aue.tdf" "add_sub_14" { Text "E:/TMP/fpga_div/db/alt_u_div_aue.tdf" 69 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_pec.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_pec.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_pec " "Info: Found entity 1: add_sub_pec" {  } { { "db/add_sub_pec.tdf" "" { Text "E:/TMP/fpga_div/db/add_sub_pec.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_pec divide0:inst\|lpm_divide:lpm_divide_component\|lpm_divide_q8p:auto_generated\|sign_div_unsign_79h:divider\|alt_u_div_aue:divider\|add_sub_pec:add_sub_15 " "Info: Elaborating entity \"add_sub_pec\" for hierarchy \"divide0:inst\|lpm_divide:lpm_divide_component\|lpm_divide_q8p:auto_generated\|sign_div_unsign_79h:divider\|alt_u_div_aue:divider\|add_sub_pec:add_sub_15\"" {  } { { "db/alt_u_div_aue.tdf" "add_sub_15" { Text "E:/TMP/fpga_div/db/alt_u_div_aue.tdf" 70 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_5dc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_5dc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_5dc " "Info: Found entity 1: add_sub_5dc" {  } { { "db/add_sub_5dc.tdf" "" { Text "E:/TMP/fpga_div/db/add_sub_5dc.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_5dc divide0:inst\|lpm_divide:lpm_divide_component\|lpm_divide_q8p:auto_generated\|sign_div_unsign_79h:divider\|alt_u_div_aue:divider\|add_sub_5dc:add_sub_2 " "Info: Elaborating entity \"add_sub_5dc\" for hierarchy \"divide0:inst\|lpm_divide:lpm_divide_component\|lpm_divide_q8p:auto_generated\|sign_div_unsign_79h:divider\|alt_u_div_aue:divider\|add_sub_5dc:add_sub_2\"" {  } { { "db/alt_u_div_aue.tdf" "add_sub_2" { Text "E:/TMP/fpga_div/db/alt_u_div_aue.tdf" 71 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_6dc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_6dc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_6dc " "Info: Found entity 1: add_sub_6dc" {  } { { "db/add_sub_6dc.tdf" "" { Text "E:/TMP/fpga_div/db/add_sub_6dc.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_6dc divide0:inst\|lpm_divide:lpm_divide_component\|lpm_divide_q8p:auto_generated\|sign_div_unsign_79h:divider\|alt_u_div_aue:divider\|add_sub_6dc:add_sub_3 " "Info: Elaborating entity \"add_sub_6dc\" for hierarchy \"divide0:inst\|lpm_divide:lpm_divide_component\|lpm_divide_q8p:auto_generated\|sign_div_unsign_79h:divider\|alt_u_div_aue:divider\|add_sub_6dc:add_sub_3\"" {  } { { "db/alt_u_div_aue.tdf" "add_sub_3" { Text "E:/TMP/fpga_div/db/alt_u_div_aue.tdf" 72 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_7dc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_7dc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_7dc " "Info: Found entity 1: add_sub_7dc" {  } { { "db/add_sub_7dc.tdf" "" { Text "E:/TMP/fpga_div/db/add_sub_7dc.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_7dc divide0:inst\|lpm_divide:lpm_divide_component\|lpm_divide_q8p:auto_generated\|sign_div_unsign_79h:divider\|alt_u_div_aue:divider\|add_sub_7dc:add_sub_4 " "Info: Elaborating entity \"add_sub_7dc\" for hierarchy \"divide0:inst\|lpm_divide:lpm_divide_component\|lpm_divide_q8p:auto_generated\|sign_div_unsign_79h:divider\|alt_u_div_aue:divider\|add_sub_7dc:add_sub_4\"" {  } { { "db/alt_u_div_aue.tdf" "add_sub_4" { Text "E:/TMP/fpga_div/db/alt_u_div_aue.tdf" 73 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_8dc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_8dc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_8dc " "Info: Found entity 1: add_sub_8dc" {  } { { "db/add_sub_8dc.tdf" "" { Text "E:/TMP/fpga_div/db/add_sub_8dc.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_8dc divide0:inst\|lpm_divide:lpm_divide_component\|lpm_divide_q8p:auto_generated\|sign_div_unsign_79h:divider\|alt_u_div_aue:divider\|add_sub_8dc:add_sub_5 " "Info: Elaborating entity \"add_sub_8dc\" for hierarchy \"divide0:inst\|lpm_divide:lpm_divide_component\|lpm_divide_q8p:auto_generated\|sign_div_unsign_79h:divider\|alt_u_div_aue:divider\|add_sub_8dc:add_sub_5\"" {  } { { "db/alt_u_div_aue.tdf" "add_sub_5" { Text "E:/TMP/fpga_div/db/alt_u_div_aue.tdf" 74 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_9dc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_9dc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_9dc " "Info: Found entity 1: add_sub_9dc" {  } { { "db/add_sub_9dc.tdf" "" { Text "E:/TMP/fpga_div/db/add_sub_9dc.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_9dc divide0:inst\|lpm_divide:lpm_divide_component\|lpm_divide_q8p:auto_generated\|sign_div_unsign_79h:divider\|alt_u_div_aue:divider\|add_sub_9dc:add_sub_6 " "Info: Elaborating entity \"add_sub_9dc\" for hierarchy \"divide0:inst\|lpm_divide:lpm_divide_component\|lpm_divide_q8p:auto_generated\|sign_div_unsign_79h:divider\|alt_u_div_aue:divider\|add_sub_9dc:add_sub_6\"" {  } { { "db/alt_u_div_aue.tdf" "add_sub_6" { Text "E:/TMP/fpga_div/db/alt_u_div_aue.tdf" 75 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_adc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_adc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_adc " "Info: Found entity 1: add_sub_adc" {  } { { "db/add_sub_adc.tdf" "" { Text "E:/TMP/fpga_div/db/add_sub_adc.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_adc divide0:inst\|lpm_divide:lpm_divide_component\|lpm_divide_q8p:auto_generated\|sign_div_unsign_79h:divider\|alt_u_div_aue:divider\|add_sub_adc:add_sub_7 " "Info: Elaborating entity \"add_sub_adc\" for hierarchy \"divide0:inst\|lpm_divide:lpm_divide_component\|lpm_divide_q8p:auto_generated\|sign_div_unsign_79h:divider\|alt_u_div_aue:divider\|add_sub_adc:add_sub_7\"" {  } { { "db/alt_u_div_aue.tdf" "add_sub_7" { Text "E:/TMP/fpga_div/db/alt_u_div_aue.tdf" 76 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_bdc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_bdc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_bdc " "Info: Found entity 1: add_sub_bdc" {  } { { "db/add_sub_bdc.tdf" "" { Text "E:/TMP/fpga_div/db/add_sub_bdc.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_bdc divide0:inst\|lpm_divide:lpm_divide_component\|lpm_divide_q8p:auto_generated\|sign_div_unsign_79h:divider\|alt_u_div_aue:divider\|add_sub_bdc:add_sub_8 " "Info: Elaborating entity \"add_sub_bdc\" for hierarchy \"divide0:inst\|lpm_divide:lpm_divide_component\|lpm_divide_q8p:auto_generated\|sign_div_unsign_79h:divider\|alt_u_div_aue:divider\|add_sub_bdc:add_sub_8\"" {  } { { "db/alt_u_div_aue.tdf" "add_sub_8" { Text "E:/TMP/fpga_div/db/alt_u_div_aue.tdf" 77 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_jec.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_jec.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_jec " "Info: Found entity 1: add_sub_jec" {  } { { "db/add_sub_jec.tdf" "" { Text "E:/TMP/fpga_div/db/add_sub_jec.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_jec divide0:inst\|lpm_divide:lpm_divide_component\|lpm_divide_q8p:auto_generated\|sign_div_unsign_79h:divider\|alt_u_div_aue:divider\|add_sub_jec:add_sub_9 " "Info: Elaborating entity \"add_sub_jec\" for hierarchy \"divide0:inst\|lpm_divide:lpm_divide_component\|lpm_divide_q8p:auto_generated\|sign_div_unsign_79h:divider\|alt_u_div_aue:divider\|add_sub_jec:add_sub_9\"" {  } { { "db/alt_u_div_aue.tdf" "add_sub_9" { Text "E:/TMP/fpga_div/db/alt_u_div_aue.tdf" 78 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_oac.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_oac.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_oac " "Info: Found entity 1: add_sub_oac" {  } { { "db/add_sub_oac.tdf" "" { Text "E:/TMP/fpga_div/db/add_sub_oac.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_oac divide0:inst\|lpm_divide:lpm_divide_component\|lpm_divide_q8p:auto_generated\|sign_div_unsign_79h:divider\|add_sub_oac:adder " "Info: Elaborating entity \"add_sub_oac\" for hierarchy \"divide0:inst\|lpm_divide:lpm_divide_component\|lpm_divide_q8p:auto_generated\|sign_div_unsign_79h:divider\|add_sub_oac:adder\"" {  } { { "db/sign_div_unsign_79h.tdf" "adder" { Text "E:/TMP/fpga_div/db/sign_div_unsign_79h.tdf" 37 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_g6f.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_g6f.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_g6f " "Info: Found entity 1: add_sub_g6f" {  } { { "db/add_sub_g6f.tdf" "" { Text "E:/TMP/fpga_div/db/add_sub_g6f.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_g6f divide0:inst\|lpm_divide:lpm_divide_component\|lpm_divide_q8p:auto_generated\|sign_div_unsign_79h:divider\|add_sub_g6f:compl_adder1 " "Info: Elaborating entity \"add_sub_g6f\" for hierarchy \"divide0:inst\|lpm_divide:lpm_divide_component\|lpm_divide_q8p:auto_generated\|sign_div_unsign_79h:divider\|add_sub_g6f:compl_adder1\"" {  } { { "db/sign_div_unsign_79h.tdf" "compl_adder1" { Text "E:/TMP/fpga_div/db/sign_div_unsign_79h.tdf" 38 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "62 " "Info: Ignored 62 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "62 " "Info: Ignored 62 SOFT buffer(s)" {  } {  } 0 0 "Ignored %1!d! SOFT buffer(s)" 0 0}  } {  } 0 0 "Ignored %1!d! buffer(s)" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "QUOTIENT\[16\] GND " "Warning: Pin \"QUOTIENT\[16\]\" stuck at GND" {  } { { "test_div.bdf" "" { Schematic "E:/TMP/fpga_div/test_div.bdf" { { -128 672 848 -112 "QUOTIENT\[0\]" "" } { -112 672 848 -96 "QUOTIENT\[1\]" "" } { -96 672 848 -80 "QUOTIENT\[2\]" "" } { -80 672 848 -64 "QUOTIENT\[3\]" "" } { -64 672 848 -48 "QUOTIENT\[4\]" "" } { -48 672 848 -32 "QUOTIENT\[5\]" "" } { -32 672 848 -16 "QUOTIENT\[6\]" "" } { -16 672 848 0 "QUOTIENT\[7\]" "" } { 0 672 848 16 "QUOTIENT\[8\]" "" } { 16 672 848 32 "QUOTIENT\[9\]" "" } { 32 672 848 48 "QUOTIENT\[10\]" "" } { 48 672 848 64 "QUOTIENT\[11\]" "" } { 64 672 848 80 "QUOTIENT\[12\]" "" } { 80 672 848 96 "QUOTIENT\[13\]" "" } { 96 672 848 112 "QUOTIENT\[14\]" "" } { 112 672 848 128 "QUOTIENT\[15\]" "" } { 128 672 848 144 "QUOTIENT\[16\]" "" } { 400 536 641 416 "QUOTIENT\[15..0\]" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "479 " "Info: Implemented 479 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "32 " "Info: Implemented 32 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "33 " "Info: Implemented 33 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "414 " "Info: Implemented 414 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jun 19 11:06:10 2008 " "Info: Processing ended: Thu Jun 19 11:06:10 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}