b     AT91F_Default_FIQ_handler
  10010c:	eafffffe 	b	10010c <AT91F_Default_FIQ_handler>00100110 <AT91F_Default_IRQ_handler>:        .size   AT91F_Default_FIQ_handler, . - AT91F_Default_FIQ_handler
        .endfunc

        .global AT91F_Default_IRQ_handler
        .func   AT91F_Default_IRQ_handler
AT91F_Default_IRQ_handler:
            b     AT91F_Default_IRQ_handler
  100110:	eafffffe 	b	100110 <AT91F_Default_IRQ_handler>00100114 <AT91F_Spurious_handler>:        .size   AT91F_Default_IRQ_handler, . - AT91F_Default_IRQ_handler
        .endfunc

        .global AT91F_Spurious_handler
        .func   AT91F_Spurious_handler
AT91F_Spurious_handler:
            b     AT91F_Spurious_handler
  100114:	eafffffe 	b	100114 <AT91F_Spurious_handler>  100118:	0010013c 	andeqs	r0, r0, ip, lsr r1  10011c:	fffff000 	swinv	0x00fff000  100120:	001003e4 	andeqs	r0, r0, r4, ror #7  100124:	00200000 	eoreq	r0, r0, r0  100128:	00200000 	eoreq	r0, r0, r0  10012c:	00200000 	eoreq	r0, r0, r0  100130:	00200000 	eoreq	r0, r0, r0  100134:	001000b8 	ldreqh	r0, [r0], -r8  100138:	00100315 	andeqs	r0, r0, r5, lsl r30010013c <AT91F_LowLevelInit>://*        this function can be use a Stack, depending the compilation
//*        optimization mode
//*----------------------------------------------------------------------------
void AT91F_LowLevelInit( void)
{
  10013c:	e1a0c00d 	mov	ip, sp  100140:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}  100144:	e24cb004 	sub	fp, ip, #4	; 0x4  100148:	e24dd008 	sub	sp, sp, #8	; 0x8 int            i;
 AT91PS_PMC     pPMC = AT91C_BASE_PMC;
  10014c:	e3a03102 	mov	r3, #-2147483648	; 0x80000000  100150:	e1a03ac3 	mov	r3, r3, asr #21  100154:	e50b3010 	str	r3, [fp, #-16]    //* Set Flash Waite sate
	//  Single Cycle Access at Up to 30 MHz, or 40
	    AT91C_BASE_MC->MC_FMR = AT91C_MC_FWS_1FWS ;
  100158:	e3e020ff 	mvn	r2, #255	; 0xff  10015c:	e3a03c01 	mov	r3, #256	; 0x100  100160:	e5823060 	str	r3, [r2, #96]
    //* Watchdog Disable
        AT91C_BASE_WDTC->WDTC_WDMR= AT91C_WDTC_WDDIS;
  100164:	e3a0332a 	mov	r3, #-1476395008	; 0xa8000000  100168:	e1a03ac3 	mov	r3, r3, asr #21  10016c:	e3a02902 	mov	r2, #32768	; 0x8000  100170:	e5832004 	str	r2, [r3, #4]
	//* Set MCK at 47 923 200
    // 1 Enabling the Main Oscillator:
        // SCK = 1/32768 = 30.51 uSecond
    	// Start up time = 8 * 6 / SCK = 56 * 30.51 = 1,46484375 ms
       //// mt pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) | AT91C_CKGR_MOSCEN ));
	   pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) ) | AT91C_CKGR_MOSCEN );
  100174:	e51b2010 	ldr	r2, [fp, #-16]  100178:	e3a03c06 	mov	r3, #1536	; 0x600  10017c:	e2833001 	add	r3, r3, #1	; 0x1  100180:	e5823020 	str	r3, [r2, #32]        // Wait the startup time
        while(!(pPMC->PMC_SR & AT91C_PMC_MOSCS));
  100184:	e51b3010 	ldr	r3, [fp, #-16]  100188:	e5933068 	ldr	r3, [r3, #104]  10018c:	e2033001 	and	r3, r3, #1	; 0x1  100190:	e3530000 	cmp	r3, #0	; 0x0  100194:	0afffffa 	beq	100184 <AT91F_LowLevelInit+0x48>	// 2 Checking the Main Oscillator Frequency (Optional)
	// 3 Setting PLL and divider:
		// - div by 14 Fin = 1.3165 =(18,432 / 14)
		// - Mul 72+1: Fout =	96.1097 =(3,6864 *73)
		// for 96 MHz the erroe is 0.11%
		// Field out NOT USED = 0
		// PLLCOUNT pll startup time estimate at : 0.844 ms
		// PLLCOUNT 28 = 0.000844 /(1/32768)
       pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 14 ) |
  100198:	e51b2010 	ldr	r2, [fp, #-16]  10019c:	e3a03712 	mov	r3, #4718592	; 0x480000  1001a0:	e2833b07 	add	r3, r3, #7168	; 0x1c00  1001a4:	e283300e 	add	r3, r3, #14	; 0xe  1001a8:	e582302c 	str	r3, [r2, #44]                         (AT91C_CKGR_PLLCOUNT & (28<<8)) |
                         (AT91C_CKGR_MUL & (72<<16)));


        // Wait the startup time
        while(!(pPMC->PMC_SR & AT91C_PMC_LOCK));
  1001ac:	e51b3010 	ldr	r3, [fp, #-16]  1001b0:	e5933068 	ldr	r3, [r3, #104]  1001b4:	e1a03123 	mov	r3, r3, lsr #2  1001b8:	e2033001 	and	r3, r3, #1	; 0x1  1001bc:	e3530000 	cmp	r3, #0	; 0x0  1001c0:	0afffff9 	beq	1001ac <AT91F_LowLevelInit+0x70>        while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));
  1001c4:	e51b3010 	ldr	r3, [fp, #-16]  1001c8:	e5933068 	ldr	r3, [r3, #104]  1001cc:	e1a031a3 	mov	r3, r3, lsr #3  1001d0:	e2033001 	and	r3, r3, #1	; 0x1  1001d4:	e3530000 	cmp	r3, #0	; 0x0  1001d8:	0afffff9 	beq	1001c4 <AT91F_LowLevelInit+0x88> 	// 4. Selection of Master Clock and Processor Clock
 	// select the PLL clock divided by 2
 	    pPMC->PMC_MCKR =  AT91C_PMC_PRES_CLK_2 ;
  1001dc:	e51b2010 	ldr	r2, [fp, #-16]  1001e0:	e3a03004 	mov	r3, #4	; 0x4  1001e4:	e5823030 	str	r3, [r2, #48] 	    while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));
  1001e8:	e51b3010 	ldr	r3, [fp, #-16]  1001ec:	e5933068 	ldr	r3, [r3, #104]  1001f0:	e1a031a3 	mov	r3, r3, lsr #3  1001f4:	e2033001 	and	r3, r3, #1	; 0x1  1001f8:	e3530000 	cmp	r3, #0	; 0x0  1001fc:	0afffff9 	beq	1001e8 <AT91F_LowLevelInit+0xac>
 	    pPMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK  ;
  100200:	e51b3010 	ldr	r3, [fp, #-16]  100204:	e5933030 	ldr	r3, [r3, #48]  100208:	e3832003 	orr	r2, r3, #3	; 0x3  10020c:	e51b3010 	ldr	r3, [fp, #-16]  100210:	e5832030 	str	r2, [r3, #48] 	    while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));
  100214:	e51b3010 	ldr	r3, [fp, #-16]  100218:	e5933068 	ldr	r3, [r3, #104]  10021c:	e1a031a3 	mov	r3, r3, lsr #3  100220:	e2033001 	and	r3, r3, #1	; 0x1  100224:	e3530000 	cmp	r3, #0	; 0x0  100228:	0afffff9 	beq	100214 <AT91F_LowLevelInit+0xd8>
	// Set up the default interrupts handler vectors
	AT91C_BASE_AIC->AIC_SVR[0] = (int) AT91F_Default_FIQ_handler ;
  10022c:	e3a03102 	mov	r3, #-2147483648	; 0x80000000  100230:	e1a039c3 	mov	r3, r3, asr #19  100234:	e59f2068 	ldr	r2, [pc, #104]	; 1002a4 <.text+0x2a4>  100238:	e5832080 	str	r2, [r3, #128]	for (i=1;i < 31; i++)
  10023c:	e3a03001 	mov	r3, #1	; 0x1  100240:	e50b3014 	str	r3, [fp, #-20]  100244:	ea00000c 	b	10027c <AT91F_LowLevelInit+0x140>	{
	    AT91C_BASE_AIC->AIC_SVR[i] = (int) AT91F_Default_IRQ_handler ;
  100248:	e3a02102 	mov	r2, #-2147483648	; 0x80000000  10024c:	e1a029c2 	mov	r2, r2, asr #19  100250:	e51b0014 	ldr	r0, [fp, #-20]  100254:	e59f304c 	ldr	r3, [pc, #76]	; 1002a8 <.text+0x2a8>  100258:	e1a0c003 	mov	ip, r3  10025c:	e3a01080 	mov	r1, #128	; 0x80  100260:	e1a03100 	mov	r3, r0, lsl #2  100264:	e0833002 	add	r3, r3, r2  100268:	e0833001 	add	r3, r3, r1  10026c:	e583c000 	str	ip, [r3]  100270:	e51b3014 	ldr	r3, [fp, #-20]  100274:	e2833001 	add	r3, r3, #1	; 0x1  100278:	e50b3014 	str	r3, [fp, #-20]  10027c:	e51b3014 	ldr	r3, [fp, #-20]  100280:	e353001e 	cmp	r3, #30	; 0x1e  100284:	daffffef 	ble	100248 <AT91F_LowLevelInit+0x10c>	}
	AT91C_BASE_AIC->AIC_SPU  = (int) AT91F_Spurious_handler ;
  100288:	e3a03102 	mov	r3, #-2147483648	; 0x80000000  10028c:	e1a039c3 	mov	r3, r3, asr #19  100290:	e59f2014 	ldr	r2, [pc, #20]	; 1002ac <.text+0x2ac>  100294:	e5832134 	str	r2, [r3, #308]
}
  100298:	e24bd00c 	sub	sp, fp, #12	; 0xc  10029c:	e89d6800 	ldmia	sp, {fp, sp, lr}  1002a0:	e12fff1e 	bx	lr  1002a4:	0010010c 	andeqs	r0, r0, ip, lsl #2  1002a8:	00100110 	andeqs	r0, r0, r0, lsl r1  1002ac:	00100114 	andeqs	r0, r0, r4, lsl r1001002b0 <Delay>:#include "include/include.h"


void Delay (unsigned long var){
  1002b0:	b580      	push	{r7, lr}  1002b2:	466f      	mov	r7, sp  1002b4:	b081      	sub	sp, #4  1002b6:	1f3b      	sub	r3, r7, #4  1002b8:	6018      	str	r0, [r3, #0]	while(--var != 0) ;
  1002ba:	1f3a      	sub	r2, r7, #4  1002bc:	1f3b      	sub	r3, r7, #4  1002be:	681b      	ldr	r3, [r3, #0]  1002c0:	3b01      	sub	r3, #1  1002c2:	6013      	str	r3, [r2, #0]  1002c4:	1f3b      	sub	r3, r7, #4  1002c6:	681b      	ldr	r3, [r3, #0]  1002c8:	2b00      	cmp	r3, #0  1002ca:	d1f6      	bne	1002ba <Delay+0xa>}
  1002cc:	46bd      	mov	sp, r7  1002ce:	bc80      	pop	{r7}  1002d0:	bc01      	pop	{r0}  1002d2:	4700      	bx	r0001002d4 <ConfigureIO>:
/*-----------------------------------------------------------------------------
 *-----------------------------------------------------------------------------*/
static void ConfigureIO (void){
  1002d4:	b580      	push	{r7, lr}  1002d6:	466f      	mov	r7, sp	// for LCD Backlight
	AT91C_BASE_PIOB->PIO_OER = (AT91B_LCD_BL);		// set to output
  1002d8:	4a0a      	ldr	r2, [pc, #40]	(100304 <.text+0x304>)  1002da:	2380      	mov	r3, #128  1002dc:	035b      	lsl	r3, r3, #13  1002de:	6113      	str	r3, [r2, #16]	AT91C_BASE_PIOB->PIO_PER = (AT91B_LCD_BL);		// set to PIO mode
  1002e0:	4a08      	ldr	r2, [pc, #32]	(100304 <.text+0x304>)  1002e2:	2380      	mov	r3, #128  1002e4:	035b      	lsl	r3, r3, #13  1002e6:	6013      	str	r3, [r2, #0]	AT91C_BASE_PIOB->PIO_PPUDR = (AT91B_LCD_BL);	// disable pull up
  1002e8:	4a06      	ldr	r2, [pc, #24]	(100304 <.text+0x304>)  1002ea:	2380      	mov	r3, #128  1002ec:	035b      	lsl	r3, r3, #13  1002ee:	6613      	str	r3, [r2, #96]
	AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_PIOA);	// enable periph clock for PIO controller
  1002f0:	4a05      	ldr	r2, [pc, #20]	(100308 <.text+0x308>)  1002f2:	2304      	mov	r3, #4  1002f4:	6113      	str	r3, [r2, #16]	AT91C_BASE_PIOA->PIO_ODR = (AT91A_JS_ALL);			// set PIO line to input
  1002f6:	4a05      	ldr	r2, [pc, #20]	(10030c <.text+0x30c>)  1002f8:	4b05      	ldr	r3, [pc, #20]	(100310 <.text+0x310>)  1002fa:	6153      	str	r3, [r2, #20]}
  1002fc:	46bd      	mov	sp, r7  1002fe:	bc80      	pop	{r7}  100300:	bc01      	pop	{r0}  100302:	4700      	bx	r0  100304:	fffff600 	bl	fff01306 <Top_Stack+0xffcf1306>  100308:	fc00      	second half of BL instruction 0xfc00  10030a:	ffff      	second half of BL instruction 0xffff  10030c:	fffff400 	bl	ffd0130e <Top_Stack+0xffaf130e>  100310:	c380      	stmia	r3!,{r7}	...00100314 <main>:
int main()
{
  100314:	b590      	push	{r4, r7, lr}  100316:	466f      	mov	r7, sp  100318:	b083      	sub	sp, #12	int cycle = 1;
  10031a:	1c3a      	mov	r2, r7		(add r2, r7, #0)  10031c:	3a0c      	sub	r2, #12  10031e:	2301      	mov	r3, #1  100320:	6013      	str	r3, [r2, #0]	const double wait = 250000;
  100322:	1c3a      	mov	r2, r7		(add r2, r7, #0)  100324:	3a08      	sub	r2, #8  100326:	4c16      	ldr	r4, [pc, #88]	(100380 <.text+0x380>)  100328:	4b14      	ldr	r3, [pc, #80]	(10037c <.text+0x37c>)  10032a:	6013      	str	r3, [r2, #0]  10032c:	6054      	str	r4, [r2, #4]
	//configure_dbgu();
	ConfigureIO();
  10032e:	ffd1f7ff 	bl	1002d4 <ConfigureIO>
	// loop forever
	while (1) {
		AT91C_BASE_PIOB->PIO_SODR = AT91B_LCD_BL;
  100332:	4a14      	ldr	r2, [pc, #80]	(100384 <.text+0x384>)  100334:	2380      	mov	r3, #128  100336:	035b      	lsl	r3, r3, #13  100338:	6313      	str	r3, [r2, #48]		Delay(wait);
  10033a:	1c3b      	mov	r3, r7		(add r3, r7, #0)  10033c:	3b08      	sub	r3, #8  10033e:	6818      	ldr	r0, [r3, #0]  100340:	6859      	ldr	r1, [r3, #4]  100342:	f84bf000 	bl	1003dc <____fixunsdfsi_from_thumb>  100346:	1c03      	mov	r3, r0		(add r3, r0, #0)  100348:	1c18      	mov	r0, r3		(add r0, r3, #0)  10034a:	ffb1f7ff 	bl	1002b0 <Delay>		AT91C_BASE_PIOB->PIO_CODR = AT91B_LCD_BL;
  10034e:	4a0d      	ldr	r2, [pc, #52]	(100384 <.text+0x384>)  100350:	2380      	mov	r3, #128  100352:	035b      	lsl	r3, r3, #13  100354:	6353      	str	r3, [r2, #52]		Delay(wait);
  100356:	1c3b      	mov	r3, r7		(add r3, r7, #0)  100358:	3b08      	sub	r3, #8  10035a:	6818      	ldr	r0, [r3, #0]  10035c:	6859      	ldr	r1, [r3, #4]  10035e:	f83df000 	bl	1003dc <____fixunsdfsi_from_thumb>  100362:	1c03      	mov	r3, r0		(add r3, r0, #0)  100364:	1c18      	mov	r0, r3		(add r0, r3, #0)  100366:	ffa3f7ff 	bl	1002b0 <Delay>		

		cycle++;	
  10036a:	1c3a      	mov	r2, r7		(add r2, r7, #0)  10036c:	3a0c      	sub	r2, #12  10036e:	1c3b      	mov	r3, r7		(add r3, r7, #0)  100370:	3b0c      	sub	r3, #12  100372:	681b      	ldr	r3, [r3, #0]  100374:	3301      	add	r3, #1  100376:	6013      	str	r3, [r2, #0]	}
  100378:	e7db      	b	100332 <main+0x1e>  10037a:	0000      	lsl	r0, r0, #0  10037c:	8480      	strh	r0, [r0, #36]  10037e:	410e      	asr	r6, r1  100380:	0000      	lsl	r0, r0, #0  100382:	0000      	lsl	r0, r0, #0  100384:	fffff600 	bl	fff01386 <Top_Stack+0xffcf1386>00100388 <__aeabi_d2uiz>:  100388:	e1b02080 	movs	r2, r0, lsl #1  10038c:	2a00000a 	bcs	1003bc <__aeabi_d2uiz+0x34>  100390:	e2922602 	adds	r2, r2, #2097152	; 0x200000  100394:	2a00000a 	bcs	1003c4 <__aeabi_d2uiz+0x3c>  100398:	5a000007 	bpl	1003bc <__aeabi_d2uiz+0x34>  10039c:	e3e03e3e 	mvn	r3, #992	; 0x3e0  1003a0:	e0532ac2 	subs	r2, r3, r2, asr #21  1003a4:	4a000008 	bmi	1003cc <__aeabi_d2uiz+0x44>  1003a8:	e1a03580 	mov	r3, r0, lsl #11  1003ac:	e3833102 	orr	r3, r3, #-2147483648	; 0x80000000  1003b0:	e1833aa1 	orr	r3, r3, r1, lsr #21  1003b4:	e1a00233 	mov	r0, r3, lsr r2  1003b8:	e12fff1e 	bx	lr  1003bc:	e3a00000 	mov	r0, #0	; 0x0  1003c0:	e12fff1e 	bx	lr  1003c4:	e1911600 	orrs	r1, r1, r0, lsl #12  1003c8:	1a000001 	bne	1003d4 <__aeabi_d2uiz+0x4c>  1003cc:	e3e00000 	mvn	r0, #0	; 0x0  1003d0:	e12fff1e 	bx	lr  1003d4:	e3a00000 	mov	r0, #0	; 0x0  1003d8:	e12fff1e 	bx	lr001003dc <____fixunsdfsi_from_thumb>:  1003dc:	4778      	bx	pc  1003de:	46c0      	nop			(mov r8, r8)001003e0 <____fixunsdfsi_change_to_arm>:  1003e0:	eaffffe8 	b	100388 <__aeabi_d2uiz>