?? at91sam7x256.h
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AT91_REG PMC_PLLR; // PLL Register
AT91_REG PMC_MCKR; // Master Clock Register
AT91_REG Reserved23[3]; //
AT91_REG PMC_PCKR[4]; // Programmable Clock Register
AT91_REG Reserved24[4]; //
AT91_REG PMC_IER; // Interrupt Enable Register
AT91_REG PMC_IDR; // Interrupt Disable Register
AT91_REG PMC_SR; // Status Register
AT91_REG PMC_IMR; // Interrupt Mask Register
AT91_REG Reserved25[36]; //
AT91_REG RSTC_RCR; // Reset Control Register
AT91_REG RSTC_RSR; // Reset Status Register
AT91_REG RSTC_RMR; // Reset Mode Register
AT91_REG Reserved26[5]; //
AT91_REG RTTC_RTMR; // Real-time Mode Register
AT91_REG RTTC_RTAR; // Real-time Alarm Register
AT91_REG RTTC_RTVR; // Real-time Value Register
AT91_REG RTTC_RTSR; // Real-time Status Register
AT91_REG PITC_PIMR; // Period Interval Mode Register
AT91_REG PITC_PISR; // Period Interval Status Register
AT91_REG PITC_PIVR; // Period Interval Value Register
AT91_REG PITC_PIIR; // Period Interval Image Register
AT91_REG WDTC_WDCR; // Watchdog Control Register
AT91_REG WDTC_WDMR; // Watchdog Mode Register
AT91_REG WDTC_WDSR; // Watchdog Status Register
AT91_REG Reserved27[5]; //
AT91_REG VREG_MR; // Voltage Regulator Mode Register
} AT91S_SYS, *AT91PS_SYS;
#else
#endif
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_AIC {
AT91_REG AIC_SMR[32]; // Source Mode Register
AT91_REG AIC_SVR[32]; // Source Vector Register
AT91_REG AIC_IVR; // IRQ Vector Register
AT91_REG AIC_FVR; // FIQ Vector Register
AT91_REG AIC_ISR; // Interrupt Status Register
AT91_REG AIC_IPR; // Interrupt Pending Register
AT91_REG AIC_IMR; // Interrupt Mask Register
AT91_REG AIC_CISR; // Core Interrupt Status Register
AT91_REG Reserved0[2]; //
AT91_REG AIC_IECR; // Interrupt Enable Command Register
AT91_REG AIC_IDCR; // Interrupt Disable Command Register
AT91_REG AIC_ICCR; // Interrupt Clear Command Register
AT91_REG AIC_ISCR; // Interrupt Set Command Register
AT91_REG AIC_EOICR; // End of Interrupt Command Register
AT91_REG AIC_SPU; // Spurious Vector Register
AT91_REG AIC_DCR; // Debug Control Register (Protect)
AT91_REG Reserved1[1]; //
AT91_REG AIC_FFER; // Fast Forcing Enable Register
AT91_REG AIC_FFDR; // Fast Forcing Disable Register
AT91_REG AIC_FFSR; // Fast Forcing Status Register
} AT91S_AIC, *AT91PS_AIC;
#else
#define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register
#define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register
#define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register
#define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register
#define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register
#define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register
#define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register
#define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register
#define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register
#define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register
#define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register
#define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register
#define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register
#define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register
#define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect)
#define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register
#define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register
#define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register
#endif
// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level
#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level
#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level
#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type
#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive
#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive
#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered
#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered
#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status
#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status
// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode
#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Peripheral DMA Controller
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_PDC {
AT91_REG PDC_RPR; // Receive Pointer Register
AT91_REG PDC_RCR; // Receive Counter Register
AT91_REG PDC_TPR; // Transmit Pointer Register
AT91_REG PDC_TCR; // Transmit Counter Register
AT91_REG PDC_RNPR; // Receive Next Pointer Register
AT91_REG PDC_RNCR; // Receive Next Counter Register
AT91_REG PDC_TNPR; // Transmit Next Pointer Register
AT91_REG PDC_TNCR; // Transmit Next Counter Register
AT91_REG PDC_PTCR; // PDC Transfer Control Register
AT91_REG PDC_PTSR; // PDC Transfer Status Register
} AT91S_PDC, *AT91PS_PDC;
#else
#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register
#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register
#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register
#define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register
#define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register
#define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register
#define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register
#define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register
#define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register
#define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register
#endif
// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable
#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable
#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable
#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable
// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Debug Unit
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_DBGU {
AT91_REG DBGU_CR; // Control Register
AT91_REG DBGU_MR; // Mode Register
AT91_REG DBGU_IER; // Interrupt Enable Register
AT91_REG DBGU_IDR; // Interrupt Disable Register
AT91_REG DBGU_IMR; // Interrupt Mask Register
AT91_REG DBGU_CSR; // Channel Status Register
AT91_REG DBGU_RHR; // Receiver Holding Register
AT91_REG DBGU_THR; // Transmitter Holding Register
AT91_REG DBGU_BRGR; // Baud Rate Generator Register
AT91_REG Reserved0[7]; //
AT91_REG DBGU_CIDR; // Chip ID Register
AT91_REG DBGU_EXID; // Chip ID Extension Register
AT91_REG DBGU_FNTR; // Force NTRST Register
AT91_REG Reserved1[45]; //
AT91_REG DBGU_RPR; // Receive Pointer Register
AT91_REG DBGU_RCR; // Receive Counter Register
AT91_REG DBGU_TPR; // Transmit Pointer Register
AT91_REG DBGU_TCR; // Transmit Counter Register
AT91_REG DBGU_RNPR; // Receive Next Pointer Register
AT91_REG DBGU_RNCR; // Receive Next Counter Register
AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
AT91_REG DBGU_TNCR; // Transmit Next Counter Register
AT91_REG DBGU_PTCR; // PDC Transfer Control Register
AT91_REG DBGU_PTSR; // PDC Transfer Status Register
} AT91S_DBGU, *AT91PS_DBGU;
#else
#define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register
#define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register
#define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register
#define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register
#define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register
#define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register
#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register
#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register
#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register
#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register
#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register
#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register
#endif
// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver
#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter
#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable
#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable
#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable
#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable
#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits
// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type
#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity
#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity
#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space)
#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark)
#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity
#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode
#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode
#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt
#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt
#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt
#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt
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