1              		.file	"Cstartup_SAM7.c"   9              	.Ltext0:  10              		.align	2  11              		.global	AT91F_LowLevelInit  13              	AT91F_LowLevelInit:  14              	.LFB2:  15              		.file 1 "init/Cstartup_SAM7.c"   1:init/Cstartup_SAM7.c **** //*----------------------------------------------------------------------------
   2:init/Cstartup_SAM7.c **** //*         ATMEL Microcontroller Software Support  -  ROUSSET  -
   3:init/Cstartup_SAM7.c **** //*----------------------------------------------------------------------------
   4:init/Cstartup_SAM7.c **** //* The software is delivered "AS IS" without warranty or condition of any
   5:init/Cstartup_SAM7.c **** //* kind, either express, implied or statutory. This includes without
   6:init/Cstartup_SAM7.c **** //* limitation any warranty or condition with respect to merchantability or
   7:init/Cstartup_SAM7.c **** //* fitness for any particular purpose, or against the infringements of
   8:init/Cstartup_SAM7.c **** //* intellectual property rights of others.
   9:init/Cstartup_SAM7.c **** //*----------------------------------------------------------------------------
  10:init/Cstartup_SAM7.c **** //* File Name           : Cstartup_SAM7.c
  11:init/Cstartup_SAM7.c **** //* Object              : Low level initializations written in C for Tools
  12:init/Cstartup_SAM7.c **** //* Creation            : 12/Jun/04
  13:init/Cstartup_SAM7.c **** //* 1.2   28/Feb/05 JPP : LIB change AT91C_WDTC_WDDIS & PLL
  14:init/Cstartup_SAM7.c **** //* 1.3   21/Mar/05 JPP : Change PLL Wait time
  15:init/Cstartup_SAM7.c **** //* 1.4   21/Aug/05 JPP : Change MC_FMR Setting
  16:init/Cstartup_SAM7.c **** //* 1.5   29/Aug/05 JPP : Change PLL error
  17:init/Cstartup_SAM7.c **** //*----------------------------------------------------------------------------
  18:init/Cstartup_SAM7.c **** 
  19:init/Cstartup_SAM7.c **** // Include the board file description
  20:init/Cstartup_SAM7.c **** #include "../include/include.h"
  21:init/Cstartup_SAM7.c **** 
  22:init/Cstartup_SAM7.c **** // The following functions must be write in ARM mode this function called directly
  23:init/Cstartup_SAM7.c **** // by exception vector
  24:init/Cstartup_SAM7.c **** extern void AT91F_Spurious_handler(void);
  25:init/Cstartup_SAM7.c **** extern void AT91F_Default_IRQ_handler(void);
  26:init/Cstartup_SAM7.c **** extern void AT91F_Default_FIQ_handler(void);
  27:init/Cstartup_SAM7.c **** 
  28:init/Cstartup_SAM7.c **** //*----------------------------------------------------------------------------
  29:init/Cstartup_SAM7.c **** //* \fn    AT91F_LowLevelInit
  30:init/Cstartup_SAM7.c **** //* \brief This function performs very low level HW initialization
  31:init/Cstartup_SAM7.c **** //*        this function can be use a Stack, depending the compilation
  32:init/Cstartup_SAM7.c **** //*        optimization mode
  33:init/Cstartup_SAM7.c **** //*----------------------------------------------------------------------------
  34:init/Cstartup_SAM7.c **** void AT91F_LowLevelInit( void)
  35:init/Cstartup_SAM7.c **** {
  16              		.loc 1 35 0  17              		@ Function supports interworking.  18              		@ args = 0, pretend = 0, frame = 8  19              		@ frame_needed = 1, uses_anonymous_args = 0  20 0000 0DC0A0E1 		mov	ip, sp  21              	.LCFI0:  22 0004 00D82DE9 		stmfd	sp!, {fp, ip, lr, pc}  23              	.LCFI1:  24 0008 04B04CE2 		sub	fp, ip, #4  25              	.LCFI2:  26 000c 08D04DE2 		sub	sp, sp, #8  27              	.LCFI3:  36:init/Cstartup_SAM7.c ****  int            i;
  37:init/Cstartup_SAM7.c ****  AT91PS_PMC     pPMC = AT91C_BASE_PMC;
  28              		.loc 1 37 0  29 0010 0231A0E3 		mov	r3, #-2147483648  30 0014 C33AA0E1 		mov	r3, r3, asr #21  31 0018 10300BE5 		str	r3, [fp, #-16]  38:init/Cstartup_SAM7.c ****     //* Set Flash Waite sate
  39:init/Cstartup_SAM7.c **** 	//  Single Cycle Access at Up to 30 MHz, or 40
  40:init/Cstartup_SAM7.c **** 	    AT91C_BASE_MC->MC_FMR = AT91C_MC_FWS_1FWS ;
  32              		.loc 1 40 0  33 001c FF20E0E3 		mvn	r2, #255  34 0020 013CA0E3 		mov	r3, #256  35 0024 603082E5 		str	r3, [r2, #96]  41:init/Cstartup_SAM7.c **** 
  42:init/Cstartup_SAM7.c ****     //* Watchdog Disable
  43:init/Cstartup_SAM7.c ****         AT91C_BASE_WDTC->WDTC_WDMR= AT91C_WDTC_WDDIS;
  36              		.loc 1 43 0  37 0028 2A33A0E3 		mov	r3, #-1476395008  38 002c C33AA0E1 		mov	r3, r3, asr #21  39 0030 0229A0E3 		mov	r2, #32768  40 0034 042083E5 		str	r2, [r3, #4]  44:init/Cstartup_SAM7.c **** 
  45:init/Cstartup_SAM7.c **** 	//* Set MCK at 47 923 200
  46:init/Cstartup_SAM7.c ****     // 1 Enabling the Main Oscillator:
  47:init/Cstartup_SAM7.c ****         // SCK = 1/32768 = 30.51 uSecond
  48:init/Cstartup_SAM7.c ****     	// Start up time = 8 * 6 / SCK = 56 * 30.51 = 1,46484375 ms
  49:init/Cstartup_SAM7.c ****        //// mt pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) | AT91C_CKGR_MOSCEN ));
  50:init/Cstartup_SAM7.c **** 	   pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) ) | AT91C_CKGR_MOSCEN );
  41              		.loc 1 50 0  42 0038 10201BE5 		ldr	r2, [fp, #-16]  43 003c 063CA0E3 		mov	r3, #1536  44 0040 013083E2 		add	r3, r3, #1  45 0044 203082E5 		str	r3, [r2, #32]  46              	.L2:  51:init/Cstartup_SAM7.c ****         // Wait the startup time
  52:init/Cstartup_SAM7.c ****         while(!(pPMC->PMC_SR & AT91C_PMC_MOSCS));
  47              		.loc 1 52 0  48 0048 10301BE5 		ldr	r3, [fp, #-16]  49 004c 683093E5 		ldr	r3, [r3, #104]  50 0050 013003E2 		and	r3, r3, #1  51 0054 000053E3 		cmp	r3, #0  52 0058 1000000A 		beq	.L2  53:init/Cstartup_SAM7.c **** 	// 2 Checking the Main Oscillator Frequency (Optional)
  54:init/Cstartup_SAM7.c **** 	// 3 Setting PLL and divider:
  55:init/Cstartup_SAM7.c **** 		// - div by 14 Fin = 1.3165 =(18,432 / 14)
  56:init/Cstartup_SAM7.c **** 		// - Mul 72+1: Fout =	96.1097 =(3,6864 *73)
  57:init/Cstartup_SAM7.c **** 		// for 96 MHz the erroe is 0.11%
  58:init/Cstartup_SAM7.c **** 		// Field out NOT USED = 0
  59:init/Cstartup_SAM7.c **** 		// PLLCOUNT pll startup time estimate at : 0.844 ms
  60:init/Cstartup_SAM7.c **** 		// PLLCOUNT 28 = 0.000844 /(1/32768)
  61:init/Cstartup_SAM7.c ****        pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 14 ) |
  53              		.loc 1 61 0  54 005c 10201BE5 		ldr	r2, [fp, #-16]  55 0060 1237A0E3 		mov	r3, #4718592  56 0064 073B83E2 		add	r3, r3, #7168  57 0068 0E3083E2 		add	r3, r3, #14  58 006c 2C3082E5 		str	r3, [r2, #44]  59              	.L4:  62:init/Cstartup_SAM7.c ****                          (AT91C_CKGR_PLLCOUNT & (28<<8)) |
  63:init/Cstartup_SAM7.c ****                          (AT91C_CKGR_MUL & (72<<16)));
  64:init/Cstartup_SAM7.c **** 
  65:init/Cstartup_SAM7.c **** 
  66:init/Cstartup_SAM7.c ****         // Wait the startup time
  67:init/Cstartup_SAM7.c ****         while(!(pPMC->PMC_SR & AT91C_PMC_LOCK));
  60              		.loc 1 67 0  61 0070 10301BE5 		ldr	r3, [fp, #-16]  62 0074 683093E5 		ldr	r3, [r3, #104]  63 0078 2331A0E1 		mov	r3, r3, lsr #2  64 007c 013003E2 		and	r3, r3, #1  65 0080 000053E3 		cmp	r3, #0  66 0084 1A00000A 		beq	.L4  67              	.L5:  68:init/Cstartup_SAM7.c ****         while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));
  68              		.loc 1 68 0  69 0088 10301BE5 		ldr	r3, [fp, #-16]  70 008c 683093E5 		ldr	r3, [r3, #104]  71 0090 A331A0E1 		mov	r3, r3, lsr #3  72 0094 013003E2 		and	r3, r3, #1  73 0098 000053E3 		cmp	r3, #0  74 009c 2000000A 		beq	.L5  69:init/Cstartup_SAM7.c ****  	// 4. Selection of Master Clock and Processor Clock
  70:init/Cstartup_SAM7.c ****  	// select the PLL clock divided by 2
  71:init/Cstartup_SAM7.c ****  	    pPMC->PMC_MCKR =  AT91C_PMC_PRES_CLK_2 ;
  75              		.loc 1 71 0  76 00a0 10201BE5 		ldr	r2, [fp, #-16]  77 00a4 0430A0E3 		mov	r3, #4  78 00a8 303082E5 		str	r3, [r2, #48]  79              	.L7:  72:init/Cstartup_SAM7.c ****  	    while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));
  80              		.loc 1 72 0  81 00ac 10301BE5 		ldr	r3, [fp, #-16]  82 00b0 683093E5 		ldr	r3, [r3, #104]  83 00b4 A331A0E1 		mov	r3, r3, lsr #3  84 00b8 013003E2 		and	r3, r3, #1  85 00bc 000053E3 		cmp	r3, #0  86 00c0 2900000A 		beq	.L7  73:init/Cstartup_SAM7.c **** 
  74:init/Cstartup_SAM7.c ****  	    pPMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK  ;
  87              		.loc 1 74 0  88 00c4 10301BE5 		ldr	r3, [fp, #-16]  89 00c8 303093E5 		ldr	r3, [r3, #48]  90 00cc 032083E3 		orr	r2, r3, #3  91 00d0 10301BE5 		ldr	r3, [fp, #-16]  92 00d4 302083E5 		str	r2, [r3, #48]  93              	.L9:  75:init/Cstartup_SAM7.c ****  	    while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));
  94              		.loc 1 75 0  95 00d8 10301BE5 		ldr	r3, [fp, #-16]  96 00dc 683093E5 		ldr	r3, [r3, #104]  97 00e0 A331A0E1 		mov	r3, r3, lsr #3  98 00e4 013003E2 		and	r3, r3, #1  99 00e8 000053E3 		cmp	r3, #0 100 00ec 3400000A 		beq	.L9  76:init/Cstartup_SAM7.c **** 
  77:init/Cstartup_SAM7.c **** 	// Set up the default interrupts handler vectors
  78:init/Cstartup_SAM7.c **** 	AT91C_BASE_AIC->AIC_SVR[0] = (int) AT91F_Default_FIQ_handler ;
 101              		.loc 1 78 0 102 00f0 0231A0E3 		mov	r3, #-2147483648 103 00f4 C339A0E1 		mov	r3, r3, asr #19 104 00f8 68209FE5 		ldr	r2, .L15 105 00fc 802083E5 		str	r2, [r3, #128]  79:init/Cstartup_SAM7.c **** 	for (i=1;i < 31; i++)
 106              		.loc 1 79 0 107 0100 0130A0E3 		mov	r3, #1 108 0104 14300BE5 		str	r3, [fp, #-20] 109 0108 4E0000EA 		b	.L11 110              	.L12:  80:init/Cstartup_SAM7.c **** 	{
  81:init/Cstartup_SAM7.c **** 	    AT91C_BASE_AIC->AIC_SVR[i] = (int) AT91F_Default_IRQ_handler ;
 111              		.loc 1 81 0 112 010c 0221A0E3 		mov	r2, #-2147483648 113 0110 C229A0E1 		mov	r2, r2, asr #19 114 0114 14001BE5 		ldr	r0, [fp, #-20] 115 0118 4C309FE5 		ldr	r3, .L15+4 116 011c 03C0A0E1 		mov	ip, r3 117 0120 8010A0E3 		mov	r1, #128 118 0124 0031A0E1 		mov	r3, r0, asl #2 119 0128 023083E0 		add	r3, r3, r2 120 012c 013083E0 		add	r3, r3, r1 121 0130 00C083E5 		str	ip, [r3, #0] 122              		.loc 1 79 0 123 0134 14301BE5 		ldr	r3, [fp, #-20] 124 0138 013083E2 		add	r3, r3, #1 125 013c 14300BE5 		str	r3, [fp, #-20] 126              	.L11: 127 0140 14301BE5 		ldr	r3, [fp, #-20] 128 0144 1E0053E3 		cmp	r3, #30 129 0148 410000DA 		ble	.L12  82:init/Cstartup_SAM7.c **** 	}
  83:init/Cstartup_SAM7.c **** 	AT91C_BASE_AIC->AIC_SPU  = (int) AT91F_Spurious_handler ;
 130              		.loc 1 83 0 131 014c 0231A0E3 		mov	r3, #-2147483648 132 0150 C339A0E1 		mov	r3, r3, asr #19 133 0154 14209FE5 		ldr	r2, .L15+8 134 0158 342183E5 		str	r2, [r3, #308]  84:init/Cstartup_SAM7.c **** 
  85:init/Cstartup_SAM7.c **** }
 135              		.loc 1 85 0 136 015c 0CD04BE2 		sub	sp, fp, #12 137 0160 00689DE8 		ldmfd	sp, {fp, sp, lr} 138 0164 1EFF2FE1 		bx	lr 139              	.L16: 140              		.align	2 141              	.L15: 142 0168 00000000 		.word	AT91F_Default_FIQ_handler 143 016c 00000000 		.word	AT91F_Default_IRQ_handler 144 0170 00000000 		.word	AT91F_Spurious_handler 145              	.LFE2: 189              	.Letext0:DEFINED SYMBOLS                            *ABS*:00000000 Cstartup_SAM7.c/cygdrive/c/DOCUME~1/Dima/LOCALS~1/Temp/ccbFSc1I.s:13     .text:00000000 AT91F_LowLevelInit/cygdrive/c/DOCUME~1/Dima/LOCALS~1/Temp/ccbFSc1I.s:20     .text:00000000 $a/cygdrive/c/DOCUME~1/Dima/LOCALS~1/Temp/ccbFSc1I.s:142    .text:00000168 $dUNDEFINED SYMBOLSAT91F_Default_FIQ_handlerAT91F_Default_IRQ_handlerAT91F_Spurious_handler