library ieee;
use ieee.std_logic_1164.all;

entity d_fre is
port
(
  clk:      in std_logic;
  D:        in std_logic;
  Q:        out std_logic
);
end;

architecture d1 of df is
--signal sig_save:      std_logic;

begin

process(clk)
begin
 if clk'event and clk='1' then
     Q<=D;
 end if;
 --Q<=sig_save;

end process;
end;