?? clk_half.vhd
字號:
--provide a 12000000Mhz frequency's clock
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
ENTITY clk_half IS
PORT(
clk : IN STD_LOGIC;
clk_out : OUT STD_LOGIC
);
END;
ARCHITECTURE fclk OF clk_half IS
signal clk_d : std_logic;
BEGIN
clk_out <= clk_d;
process(clk)
begin
if rising_edge(clk) then
clk_d<=not clk_d;
end if;
end process;
end;
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -