--provide a 12000000Mhz frequency's clock


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
ENTITY clk_half IS
    PORT(
        clk             : IN    STD_LOGIC;
        clk_out         : OUT   STD_LOGIC
         );
END;

ARCHITECTURE fclk OF clk_half IS
     
   signal clk_d      : std_logic;    
BEGIN

clk_out <= clk_d;

process(clk)
	begin
		if rising_edge(clk) then
		
				clk_d<=not clk_d;
          
        end if;
end process;

end;