library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity bcd is
	PORT(
		clk                          : in      std_logic;
		data_in                      : in      std_logic_vector(7 downto 0);
		out_a,out_b,out_c            : out     std_logic_vector(4 downto 0)
		);
end;

ARCHITECTURE behave of bcd is
	
	TYPE TRANSF_TYPE IS (t0,t1,t2,t3);
	signal state_transf: TRANSF_TYPE;
	
    signal data_transf_buff     : std_logic_vector(7 downto 0);
    signal transfed_buff        : std_logic_vector(4 downto 0);
    signal a,b,c                : std_logic_vector(3 downto 0);

begin

-----------------------------transfrom_code-------------------------------------
process (clk,state_transf)

	begin
		if clk 'event and clk ='1' then
			case state_transf is
			
				when t0 =>
				    transfed_buff <= "00000";
				    a <= "0000";
				    data_transf_buff <= data_in; 
                    state_transf<=t1;

				when t1 =>
				    if data_transf_buff >= "00001010" then
				          data_transf_buff <= data_transf_buff - "00001010";    
				          transfed_buff <= transfed_buff + 1;
				          state_transf<=t1;
				    else  c <= data_transf_buff(3 downto 0);
				          state_transf<=t2; 
				    end if;
				
				when t2 =>
				    if transfed_buff >= "01010" then
				          transfed_buff <= transfed_buff - "01010";    
				          a <= a + 1;
				          state_transf<=t2;
				    else  
				          b <=transfed_buff(3 downto 0);
				          state_transf<=t3; 
				    end if;
				when t3 =>
				    out_a <= '0'&a;
                    out_b <= '0'&b;
                    out_c <= '0'&c;
                    state_transf <= t0;
			end case;
		end if;
end process;

end behave;