#AD 80C196K? 100#
#AD 80C196K? 101#
#AD 80C196K? 102#
#AD 80C196K? 103#
#AD 80C196K? 104#
#AD 80C196K? 105#
#AD 80C196K? 106#
#AD 80C196K? 107#
Select the desired A/D channel.

The Analog-to-Digital Converter can perform conversions on one of eight
channels.

The channel number that you select will be written to AD_COMMAND.0-AD_COMMAND.2.
#AD 80C198 100#
#AD 80C198 101#
#AD 80C198 102#
#AD 80C198 103#
Select the desired A/D channel.

The Analog-to-Digital Converter can perform conversions on one of four 
channels.

The channel number that you select will be written to AD_COMMAND.0-AD_COMMAND.2.
#AD 80C196K? 200#
#AD 80C19? 200#
This field determines whether analog-to-digital conversions are started
immediately or are triggered by the HSO unit.

The AD Conversion Source bit (AD_COMMAND.3) determines when an
analog-to-digital conversion is to start.  Checking "Start Now" sets
AD_COMMAND.3; clearing "Start Now" clears AD_COMMAND.3.
#AD 80C196KB 501#
#AD 80C19? 501#
#AD 80C196KB 502#
#AD 80C19? 502#
Determine whether to configure the Analog-to-Digital Converter for normal or
fast mode.

The normal mode uses 15 state times for the sample time and a total of 158
state times for the entire conversion.

The fast mode uses 8 state times for the sample time and a total of 91
state times for the conversion.

Selecting "Fast" sets IOC2.4.  Selecting "Normal" clears IOC2.4.
#AD 80C196KC 501#
#AD 80C196KD 501#
#AD 80C196KC 502#
#AD 80C196KD 502#
Determine whether to configure the Analog-to-Digital converter for normal or
fast mode.

The normal mode uses 15 state times for the sample time and a total of 158
state times for the entire conversion.

The fast mode uses 8 state times for the sample time and a total
of 91 state times for the conversion.

Note:  The fast and normal modes are available only when the 80C196KB-
compatible option is selected.  Otherwise the A/D conversion speed is
determined by the entered sample and convert times.

Selecting "Fast" sets IOC2.4.  Selecting "Normal" clears IOC2.4.
#AD 80C196K? 600#
#AD 80C19? 600#
Select this option to enable the A/D-Conversion-Complete interrupt.

The A/D Converter causes an A/D-Conversion-Complete pending interrupt when it
completes a conversion.  If this interrupt is enabled, the pending interrupt
will be generated.

The A/D-Conversion-Complete interrupt is enabled by setting INT_MASK.1.
#AD 80C196K? 301#
#AD 80C196K? 300#
The Analog-to-Digital Converter can perform 8- or 10-bit conversions.  Use this
field to configure the converter for 8- or 10-bit conversions.

The AD Conversion Mode bit (AD_COMMAND.4) determines whether 8- or 10-bit
conversions are performed.  Selecting "8-bit Conversion" sets AD_COMMAND.4.
Selecting "10-bit Conversion" clears AD_COMMAND.4.
#AD 80C196K? 400#
#AD 80C196K? 401#
Determine whether the conversion times are 80C196KB-Compatible or are
independently configurable.

When the 80C196KB-compatible mode is selected, the conversion speed is
determined by the fast and normal options.

When the configurable mode is selected, the conversion speed is determined by
the sample and convert time options.

Selecting "Configurable" sets IOC2.3.  Selecting "80C196KB-Compatible" clears
IOC2.3.
#AD 80C196K? 701#
Enter the sample time in microseconds.

Acceptable sample times are:

Sample time (minimum) = 10 / Fosc
Sample time (maximum) = 58 / Fosc
#AD 80C196?? 801#
Enter the conversion time in microseconds.

Acceptable conversion times are:

For 8-bit conversions,
Conversion time (minimum) = 51 / Fosc
Conversion time (maximum) = 515 / Fosc

For 10-bit conversions,
Conversion time (minimum) = 63 / Fosc
Conversion time (maximum) = 643 / Fosc
#PWM 80C196KB 100#
#PWM 80C19? 100#
#PWM? 80C196K? 100#
#PWM? 80C19? 100#
Select this option for a PWM period of 256 state times.

The PWM clock prescaler is controlled by IOC2.2.  Selecting "Divide by 1"
clears IOC2.2.
#PWM 80C196KB 101#
#PWM 80C19? 101#
#PWM? 80C196K? 101#
#PWM? 80C19? 101#
Select this option for a PWM period of 512 state times.

The PWM clock prescaler is controlled by IOC2.2.  Selecting "Divide by 2"
sets IOC2.2.
#PWM 80C196KB 200#
#PWM 80C19? 200#
#PWM? 80C196K? 200#
Select this option to enable the PWM0 output.

The PWM0 output is multiplexed with the P2.5 pin. Selecting the PWM 0 output
function disables the port function.
#PWM 80C196KB 300#
#PWM 80C19? 300#
#PWM0 80C196K? 300#
#PWM1 80C196K? 301#
#PWM2 80C196K? 302#
Enter the PWM duty cycle percentage.

Entering a value in this field also updates the Control Register field. The
PWM control register equals 256 * (duty cycle%).
#PWM 80C196KB 400#
#PWM 80C19? 400#
#PWM0 80C196K? 400#
Enter a value between 0 and 255.

The PWM0 Control Register, in conjunction with the PWM prescaler, determines
how long the PWM output is held high during the pulse, effectively controlling
the duty cycle.  The value written to the PWM0 Control Register can be from 0
to 255 state times (0% to 99.6% duty cycle).

Entering a value in this field also updates the Duty Cycle field. The duty cycle
equals (PWM Control Register) / 256.
#PWM1 80C196K? 201#
Select this option to enable the PWM 1 Output.

The PWM1 output is multiplexed with the P1.3 pin.  Selecting the PWM1 output
function disables the quasi-bidirectional Port 1 function and enables strong
pull-ups and pull-downs.
#PWM1 80C196K? 401#
Enter a value between 0 and 255.

The PWM1 Control Register, in conjunction with the PWM prescaler, determines
how long the PWM output is held high during the pulse, effectively controlling
the duty cycle.  The value written to the PWM1 Control Register can be from 0
to 255 state times (0% to 99.6% duty cycle).

Entering a value in this field also updates the Duty Cycle field. The duty cycle
equals (PWM Control Register) / 256.
#PWM2 80C196K? 202#
Select this option to enable the PWM 2 Output.

The PWM2 output is multiplexed with the P1.4 pin.  Selecting the PWM2 output
function disables the quasi-bidirectional Port 1 function and enables strong
pull-ups and pull-downs.
#PWM2 80C196K? 402#
Enter a value between 0 and 255.

The PWM2 Control Register, in conjunction with the PWM prescaler, determines
how long the PWM output is held high during the pulse, effectively controlling
the duty cycle.  The value written to the PWM2 Control Register can be from 0
to 255 state times (0% to 99.6% duty cycle).

Entering a value in this field also updates the Duty Cycle field. The duty cycle
equals (PWM Control Register) / 256.
#Serial 80C196K? 100#
#Serial 80C19? 100#
Select this option to enable the Transmit interrupt.

During a serial transmission, the TI flag is set at the beginning of the stop
bit.  When the TI flag is set, a pending transmit interrupt occurs.  If the
interrupt is enabled, the interrupt signal is generated.
#Serial 80C196K? 101#
#Serial 80C19? 101#
Select this option to enable the Receive interrupt.

During a serial reception in Modes 0, 1, and 3, the RI flag is set just after
the end of the stop bit.  When the RI flag is set, a pending receive interrupt
occurs.  If the interrupt is enabled, the interrupt signal is generated.

In Mode 2, the receive interrupt is generated only if the ninth data bit is
set.
#Serial 80C196K? 102#
#Serial 80C19? 102#
Select this option to enable the Serial interrupt.

If 8096BH compatibility is desired, transmit and receive events can both
generate the Serial Port Interrupt.  During a serial transmission, the TI flag
is set at the beginning of the stop bit; during a serial reception, the RI
flag is set just after the end of the stop bit. When either the RI or the TI 
flag is set, a pending serial interrupt occurs.  If the serial interrupt is
enabled, the interrupt signal is generated.  The Serial Port Status Register 
can then be read to determine whether a transmission or reception caused the 
interrupt.

In Mode 2, the serial interrupt is generated only if the ninth data bit is
set.
#Serial 80C196K? 200#
#Serial 80C19? 200#
Select this option to enable parity (Modes 1 and 3 only).

Mode 1 - If parity is enabled, an even parity bit is sent instead of the eighth
data bit, and parity is checked on reception.

Mode 3 - If parity is enabled, an even parity bit is sent instead of the ninth
data bit and the Serial Port Status Register contains a Receive Parity Error bit.
#Serial 80C196K? 202#
#Serial 80C19? 202#
#Serial 80C196K? 203#
#Serial 80C19? 203#
Determine the value of the 9th data bit (Modes 2 and 3 only).

Operations in Modes 2 and 3 use data frames consisting of 11 bits: one start
bit, 9 data bits, and one stop bit.  When parity is enabled in Mode 3, the
ninth data bit becomes the even parity bit.

For Mode 2 and Mode 3 (parity disabled), the desired value of the ninth data
bit is written to the TB8 (transmit bit eight) bit in the Serial Port Control
Register.  During a reception, the ninth data bit is read in the Serial Port
Status Register.

In Mode 2, during a reception, the RI flag is set and an interrupt is generated
only if the ninth data bit is set.
#Serial 80C196K? 300#
#Serial 80C19? 300#
This option selects an internal clock source for the baud-rate generator.

When an internal clock source is selected, the XTAL1 input signal (Fosc)
becomes the clock input into the baud-rate generator.
#Serial 80C196K? 301#
#Serial 80C19? 301#
This option selects an external clock source for the baud-rate generator.

When an external clock source is selected, the external signal on the T2CLK pin
becomes the clock input into the baud-rate generator.  The maximum T2CLK input
frequency is Fosc/4.
#Serial 80C196K? 500#
#Serial 80C19? 500#
Select the desired baud rate for all serial I/O modes.

Maximum Baud Rate:
Mode  Internal Clock External Clock
0  Fosc / 2    T2CLK frequency
1, 2, 3  Fosc / 16      T2CLK frequency / 8
#Serial 80C196K? 501#
#Serial 80C19? 501#
Select this option to enable the RXD pin.

In Modes 1, 2, and 3, RXD is used to receive serial port data.  In Mode 0, it
functions as an input or an open-drain output for data.
#Serial 80C196K? 502#
#Serial 80C19? 502#
Select this option to enable the TXD pin.

In Modes 1, 2, and 3, TXD is used to transmit serial port data.  In Mode 0, it
is used as the serial clock output.
#Serial 80C196K? 600#
#Serial 80C19? 600#
This option selects the Synchronous 8-bit Serial Mode.

In this mode, the TXD pin outputs a set of eight clock pulses, while the RXD
pin either transmits or receives data.  Data is transferred eight bits at a
time with the least-significant bit first.
#Serial 80C196K? 601#
#Serial 80C19? 601#
This option selects the Asynchronous 8-bit Serial Mode.

Mode 1 is the standard 8-bit, asynchronous mode used for normal serial
communications.  Modes 1, 2, and 3 are full-duplex serial transmit/receive
modes, meaning that they can transmit and receive data
simultaneously.
#Serial 80C196K? 602#
#Serial 80C19? 602#
This option selects the Asynchronous Ninth-bit Recognition Serial Mode.

Mode 2 is a 9-bit asynchronous mode typically used for interprocessor
communications.  In this mode, a serial reception generates an interrupt only
if the ninth data bit is set.  The Mode 2 data frame consists of a start bit
(0), nine data bits (LSB first), and a stop bit (1).  Parity cannot be enabled
in the mode.
#Serial 80C196K? 603#
#Serial 80C19? 603#
This option selects the Asynchronous 9-bit Serial Mode.

The Mode 3 data frame consists of a start bit (0), nine data bits (LSB first),
and a stop bit (1).  In Mode 3, the serial port always generates an interrupt
upon completion of a data transmission or reception.  If parity is enabled, the
ninth data bit becomes the even parity bit.
#BIU 80C196K? 101#
#BIU 80C19? 101#
#CODE 80C196K? 101#
#CODE 80C19? 101#