#PM 80C196K? 101#
#PM 80C19? 101#
#BIU 80C196K? 102#
#BIU 80C19? 102#
#CODE 80C196K? 102#
#CODE 80C19? 102#
#PM 80C196K? 102#
#PM 80C19? 102#
#BIU 80C196K? 103#
#BIU 80C19? 103#
#CODE 80C196K? 103#
#CODE 80C19? 103#
#PM 80C196K? 103#
#PM 80C19? 103#
Select the desired number of wait states.

Wait states are inserted into the bus cycle either until the READY pin is
pulled high or until this internal number is reached.
#BIU 80C196K? 104#
#BIU 80C19? 104#
#CODE 80C196K? 104#
#CODE 80C19? 104#
#PM 80C196K? 104#
#PM 80C19? 104#
When this option is selected, wait states are inserted into the bus cycle until
the READY pin is pulled high.
#BIU 80C196K? 203#
#BIU 80C19? 203#
#CODE 80C196K? 203#
#CODE 80C19? 203#
#PM 80C196K? 203#
#PM 80C19? 203#
This option selects the Standard Bus mode.

The standard bus mode uses a 16-bit multiplexed address/data bus.  In this
mode, external memory is addressed through lines AD0-AD15, which form a 16-bit
multiplexed bus.  The address/data bus shares pins with ports 3 and 4.
#BIU 80C196K? 202#
#BIU 80C19? 202#
#CODE 80C196K? 202#
#CODE 80C19? 202#
#PM 80C196K? 202#
#PM 80C198 202#
This option selects the Write Strobe mode.

The Write Strobe mode eliminates the need to externally decode high- and
low-byte writes to external 16-bit RAM in 16-bit bus mode.
#BIU 80C196K? 201#
#BIU 80C19? 201#
#CODE 80C196K? 201#
#CODE 80C19? 201#
#PM 80C196K? 201#
#PM 80C19? 201#
This option selects the Address Valid Strobe mode.

When the Address Valid Strobe mode is selected, the device generates the
Address Valid signal (ADV#) instead of the Address Latch Enable signal (ALE).
ADV# is asserted after an external address is valid.  This signal can be used
to latch the valid address and simultaneously enable an external memory
device.
#BIU 80C196K? 200#
#BIU 80C19? 200#
#CODE 80C196K? 200#
#CODE 80C19? 200#
#PM 80C196K? 200#
#PM 80C19? 200#
This option selects the Address Valid with Write Strobe mode.

When the Address Valid with Write Strobe mode is selected, the device
generates the ADV#, WRL#, and WRH# bus-control signals. This mode is used for
a simple system using external 16-bit RAM.
#BIU 80C196K? 300#
#BIU 80C19? 300#
#CODE 80C196K? 300#
#CODE 80C19? 300#
#PM 80C196K? 300#
#PM 80C19? 300#
#BIU 80C196K? 301#
#BIU 80C19? 301#
#CODE 80C196K? 301#
#CODE 80C19? 301#
#PM 80C196K? 301#
#PM 80C19? 301#
Determine whether to enable or disable the bus-hold protocol.

The device supports a bus-hold protocol that allows external devices to gain
control of the address/data bus.
#BIU 80C196K? 401#
#BIU 80C19? 401#
#CODE 80C196K? 401#
#CODE 80C19? 401#
#PM 80C196K? 401#
#PM 80C19? 401#
#BIU 80C196K? 402#
#BIU 80C19? 402#
#CODE 80C196K? 402#
#CODE 80C19? 402#
#PM 80C196K? 402#
#PM 80C19? 402#
#BIU 80C196K? 400#
#BIU 80C196? 400#
#CODE 80C196K? 400#
#CODE 80C19? 400#
#PM 80C196K? 400#
#PM 80C19? 400#
#BIU 80C196K? 403#
#BIU 80C19? 403#
#CODE 80C19K? 403#
#CODE 80C19? 403#
#PM 80C196K? 403#
#PM 80C19? 403#
Select a programming protection scheme for internal memory.

This device supports three protection schemes; read/write protection, write-
only protection and read-only protection. The Chip Configuration register
controls the protection scheme.
#BIU 80C196K? 501#
#BIU 80C19? 501#
#CODE 80C196K? 501#
#CODE 80C19? 501#
#PM 80C196K? 501#
#PM 80C19? 501#
#BIU 80C196K? 502#
#BIU 80C19? 502#
#CODE 80C196K? 502#
#CODE 80C19? 502#
#PM 80C196K? 502#
#PM 80C19? 502#
Determine the bus width.

The external bus width can be run-time configured to operate as a 16-bit
multiplexed address/data bus or a multiplexed 16-bit address/8-bit data bus.
#BIU 80C196K? 600#
#BIU 80C19? 600#
#CODE 80C196K? 600#
#CODE 80C19? 600#
#PM 80C196K? 600#
#PM 80C19? 600#
Check this box to enable Powerdown mode.

When Powerdown mode is enabled, the IDLPD #2 instruction causes the device
to enter Powerdown mode.
#Timer1 80C196K? 100#
#Timer1 80C19? 100#
Select this option to enable the Timer Overflow Interrupt.

When Timer 1 overflows, it will generate a Timer Overflow interrupt only if
both the Timer 1 overflow detection is enabled (IOC1.2=1) and the Timer
Overflow interrupt is enabled (INT_MASK.0=1).
#Timer1 80C196K? 200#
#Timer1 80C19? 200#
Select this option to enable the Timer 1 overflow detection.

When Timer 1 overflows it will generate a Timer Overflow interrupt only if
both the Timer 1 overflow detection is enabled (IOC1.2=1) and the Timer
Overflow interrupt is enabled (INT_MASK.0=1).
#Timer2 80C196KB 101#
#Timer2 80C19? 101#
#Timer2 80C196K? 102#
#Timer2 80C19? 102#
Timer 2 is clocked externally.  You may select either the T2CLK or HSI.1 pin
as the clock source.
#Timer2 80C196KC 101#
#Timer2 80C196KD 101#
Timer 2 can be clocked either internally or externally.  When external
clocking is selected, you may select either the T2CLK or HSI.1 pin as the
clock source.
#Timer2 80C196KC 103#
#Timer2 80C196KD 103#
Timer 2 can be clocked either internally or externally.  When internal
clocking is selected Fosc/16 is the clocking frequency.
#Timer2 80C196K? 201#
#Timer2 80C19? 201#
Select this option to configure Timer 2 for up counting only.
#Timer2 80C196K? 202#
Select this option to enable the Timer 2 Up/Down function.

When the Up/Down function is enabled (IOC2.1=1), Timer 2 counts either up or
down depending upon the value of the T2UP-DN pin.  If IOC2.1 is set and
T2UP-DN is high, Timer 2 counts up.  If IOC2.1 is set and T2UP-DN is low,
Timer 2 counts down.  The T2UP-DN signal must be stable either before or at
the same time that the T2CLK signal changes, to ensure that the timer will
change direction during the next clock period.
#Timer2 80C196K? 301#
#Timer2 80C19? 301#
#Timer2 80C196K? 302#
#Timer2 80C19? 302#
Determine whether Timer 2 is configured for fast increment mode or normal
increment mode.

The Fast Timer 2 enable bit in the IOC2 register (IOC2.0) controls whether
Timer 2 counts every clock (fast increment mode) or every eight clocks (normal
mode).
#Timer2 80C196K? 401#
#Timer2 80C19? 401#
This option selects the T2RST pin as the Timer 2 reset source.

Timer 2 can be reset by hardware, software, or the HSO module.  Setting the
Timer 2 Reset enable bit (IOC0.3) enables an external reset source.  Setting
the Timer 2 Reset Source bit (IOC0.5) selects the HSI.0 pin and clearing it
selects the T2RST (P2.4) pin as the external Timer 2 reset signal.
#Timer2 80C196K? 402#
#Timer2 80C19? 402#
This option selects the HSI.0 pin as the Timer 2 reset source.

Timer 2 can be reset by hardware, software, or the HSO module.  Setting the
Timer 2 Reset enable bit (IOC0.3) enables an external reset source.  Setting
the Timer 2 Reset Source bit (IOC0.5) selects the HSI.0 pin and clearing it
selects the T2RST (P2.4) pin as the external Timer 2 reset signal.
#Timer2 80C196K? 403#
#Timer2 80C19? 403#
Timer 2 can be reset by hardware, software, or the HSO module. Selecting this
option disables external Timer 2 reset sources.
#Timer2 80C196K? 501#
#Timer2 80C19? 501#
Select this option to have Timer 2 reset after each write.

Software can reset Timer 2 by setting the Timer 2 Software Reset bit in the
I/O Control 0 Register.
#Timer2 80C196K? 601#
#Timer2 80C19? 601#
#Timer2 80C196K? 602#
#Timer2 80C19? 602#
Determine the Timer 2 overflow interrupt boundary.

Timer 2 can generate the Timer 2 overflow interrupt at either the 0FFFFH/0000H
or the 7FFFH/8000H boundary.  An overflow can occur in either direction.
#Timer2 80C196K? 701#
#Timer2 80C19? 701#
Select this option to enable the Timer 2 overflow detection.

Both Timer 1 and Timer 2 have overflow detection enable bits in the I/O
Control 1 Register.  When Timer 2 overflows, it will generate a pending Timer
Overflow interrupt only if its overflow detection bit is set. If the Timer
Overflow interrupt is enabled, the interrupt will be generated.
#Timer2 80C196K? 801#
#Timer2 80C19? 801#
Select this option to enable the Timer 2 Overflow interrupt.

Timer 2 can generate the Timer 2 Overflow interrupt instead of the standard
Timer Overflow interrupt.  This interrupt is enabled by setting INT_MASK1.4.
#Timer2 80C196K? 802#
#Timer2 80C19? 802#
Select this option to enable the Timer Overflow interrupt.  In order for Timer
2 to generate this interrupt, its timer overflow detection bit must be set
(IOC1.3=1).  Both Timer 1 and Timer 2 can generate the Timer Overflow
interrupt.  When a timer overflows, the I/O Status 1 Register can be read to
determine which timer overflowed.
#Timer2 80C196K? 803#
Select this option to enable the Timer 2 Capture interrupt.

A positive transition on the T2CAPTURE pin causes the value of Timer 2 to be
loaded into the T2CAPTURE register.  This event generates a Timer 2 Capture
pending interrupt. If the Timer 2 Capture interrupt is enabled, the interrupt
will be generated.
#HSI? 80C196K? 100#
#HSI? 80C19? 100#
Select this option to enable the HSI input function.

You can individually enable or disable the HSI input function of each HSI pin
by setting or clearing the corresponding bit in the IOC0 register.
#HSI0 80C196K? 200#
#HSI0 80C19? 200#
This option configures the HSI module to capture every eighth positive
transition on the HSI.0 pin.  When a transition is detected, the Timer 1 value
is written to the HSI Time Register.
#HSI1 80C196K? 200#
#HSI1 80C19? 200#
This option configures the HSI module to capture every eighth positive
transition on the HSI.1 pin.  When a transition is detected, the Timer 1 value
is written to the HSI Time Register.
#HSI2 80C196K? 200#
#HSI2 80C19? 200#
This option configures the HSI module to capture every eighth positive
transition on the HSI.2 pin.  When a transition is detected, the Timer 1 value
is written to the HSI Time Register.
#HSI3 80C196K? 200#
#HSI3 80C19? 200#
This option configures the HSI module to capture every eighth positive
transition on the HSI.3 pin.  When a transition is detected, the Timer 1 value
is written to the HSI Time Register.
#HSI0 80C196K? 201#
#HSI0 80C19? 201#
This option configures the HSI module to capture each positive transition on
the HSI.0 pin.  When a transition is detected, the Timer 1 value is written to
the HSI Time Register.
#HSI1 80C196K? 201#
#HSI1 80C19? 201#
This option configures the HSI module to capture each positive transition on
the HSI.1 pin.  When a transition is detected, the Timer 1 value is written to
the HSI Time Register.
#HSI2 80C196K? 201#
#HSI2 80C19? 201#
This option configures the HSI module to capture each positive transition on
the HSI.2 pin.  When a transition is detected, the Timer 1 value is written to
the HSI Time Register.
#HSI3 80C196K? 201#
#HSI3 80C19? 201#
This option configures the HSI module to capture each positive transition on
the HSI.3 pin.  When a transition is detected, the Timer 1 value is written to
the HSI Time Register.
#HSI0 80C196K? 202#
#HSI0 80C19? 202#
This option configures the HSI module to capture each negative transition on
the HSI.0 pin.  When a transition is detected, the Timer 1 value is written to
the HSI Time Register.
#HSI1 80C196K? 202#
#HSI1 80C19? 202#
This option configures the HSI module to capture each negative transition on
the HSI.1 pin.  When a transition is detected, the Timer 1 value is written to
the HSI Time Register.
#HSI2 80C196K? 202#
#HSI2 80C19? 202#
This option configures the HSI module to capture each negative transition on
the HSI.2 pin.  When a transition is detected, the Timer 1 value is written to
the HSI Time Register.