#AD 80C196?? 200#
#AD 80C296?? 200#
This field determines whether analog-to-digital conversions are started
immediately or are triggered by the EPA unit.

The AD Conversion Source bit in the AD_COMMAND register determines when an
analog-to-digital conversion is to start.
#AD 80C196?? 600#
#AD 80C296?? 600#
Select this option to enable the A/D Conversion Complete interrupt.

The A/D Converter causes an A/D Conversion Complete pending interrupt when it
completes a conversion.  If this interrupt is enabled, the pending interrupt
will be generated.
#AD 80C196?? 300#
#AD 80C296?? 300#
#AD 80C196?? 301#
#AD 80C296?? 301#
#AD 80C196?? 302#
#AD 80C296?? 302#
#AD 80C196?? 303#
#AD 80C296?? 303#
Select the conversion mode.

The Analog-to-Digital Converter can perform 8- or 10-bit conversions, or it can
detect a threshold voltage on one of its input channels.
#AD 80C196?? 701#
#AD 80C296?? 701#
Enter the sample time in microseconds.

Acceptable sample times are:

Sample time (minimum) = 10 / Fosc
Sample time (maximum) = 58 / Fosc
#AD 80C196?? 801#
#AD 80C296?? 801#
Enter the conversion time in microseconds.

Acceptable conversion times are:

For 8-bit conversions,
Conversion time (minimum) = 51 / Fosc
Conversion time (maximum) = 515 / Fosc

For 10-bit conversions,
Conversion time (minimum) = 63 / Fosc
Conversion time (maximum) = 643 / Fosc
#AD 80C196?? 900#
#AD 80C296?? 900#
Select the zero offset adjustment.

No offset voltage is added to the resistor ladder and applies to all input
channels.
#AD 80C196?? 901#
#AD 80C296?? 901#
Select the zero offset adjustment.

This offset voltage is added to the resistor ladder and applies to all input
channels.
#AD 80C196?? 902#
#AD 80C296?? 902#
#AD 80C196?? 903#
#AD 80C296?? 903#
Select the zero offset adjustment.

This offset voltage is subtracted from the resistor ladder and applies to all input
channels.
#AD 80C196?? 904#
#AD 80C296?? 904#
Select the zero offset adjustment.

Calculates and sets the offset voltage by converting ANGND and minimizing
error.
#AD 80C196?? 905#
#AD 80C296?? 905#
Select the zero offset adjustment.

Calculates and sets the offset voltage by converting VREF and minimizing
error.
#AD 80C196?? 1000#
#AD 80C296?? 1000#
Enter the VREF voltage.

Valid voltages are between 4.5 and 5.5 volts.
#AD 80C196?? 1001#
#AD 80C296?? 1001#
Enter the ANGND voltage.

Valid voltages are between -0.05 and +0.05 volts.
#AD 80C196?? 1010#
#AD 80C296?? 1010#
#AD 80C196?? 1011#
#AD 80C296?? 1011#
Enter either the threshold value or the threshold voltage.  The threshold
value is written to the high byte of the A/D Result register.  The threshold
value is determined from a given threshold voltage by the following equation:

threshold value = 256 * (threshold voltage) / (VREF - ANGND)

This field is used when the A/D Converter is configured for one of the
threshold detection modes.  When the voltage on the analog input pin crosses
over (detect high) or under (detect low) the threshold value, the A/D
Conversion Complete interrupt flag is set.
#AD 80C196J? 1030#
#AD 80C196N? 1030#
Select the desired A/D channel.

The Analog-to-Digital Converter can perform conversions on one of four
channels.

The channel number that you select will be written to AD_COMMAND.0-AD_COMMAND.2.
#AD 80C196K? 1030#
Select the desired A/D channel.

The Analog-to-Digital Converter can perform conversions on one of eight
channels.

The channel number that you select will be written to AD_COMMAND.0-AD_COMMAND.2.
#CPU 80C196NU 950#
#CPU 80C296?? 950#
#PM 80C196NU 950#
Checking this option enables the SATURATION enable mode of the accumulator.

When saturation enable mode is enabled, saturation will occure when 2 positave numbers generate a negitave sign bit, or 2 negitave numbers generate a positive sign bit.
Saturation will not occure when the sign bits of the operands are different.

In saturation mode, the accumulated value will be allowed to overflow or underflow.
If saturation mode is not enabled, on overflow of underflow occurs and the overflow flag will be set.
#CPU 80C296?? 990#
The Embedded Signal Processing button will take you to a dialog where you can set
up the Index registers IDX0 and IDX1 along with their associated auto-increment/decrement
registers ICB0 and ICB1.  The enabling of fractional mode and saturation mode is also
handled in this area.
#CPU 80C196NU 951#
#CPU 80C296?? 951#
#PM 80C196NU 951#
Checking this option enables the FRACTIONAL enable mode of the accumulator.
Fractional mode is set to allow operation on fractional data.
#CPU 80C196NU 150#
#CPU 80C296?? 150#
#PM 80C196NU 150#
Checking this option enables the deferred mode.

Deferred mode extends the bus cycle (by 2T) whenever a chip select change or a read cycle is followed by a write cycle in demultiplaxed mode.  This allows slower RAM to be accessed without bus conflicts.
#CPU 80C196NP 901#
#BIU 80C196NP 901#
#CODE 80C196NP 901#
#PM 80C196NP 901#
#CPU 80C196NU 901#
#CPU 80C296?? 901#
#PM 80C196NU 901#
Select this option for a 16-bit program counter for 64-Kbyte addressing.
#CPU 80C196NP 900#
#BIU 80C196NP 900#
#CODE 80C196NP 900#
#PM 80C196NP 900#
#CPU 80C196NU 900#
#CPU 80C296?? 900#
#PM 80C196NU 900#
Select this option for a 24-bit program counter for 1-Mbyte addressing.
#CPU 80C196NP 905#
#BIU 80C196NP 905#
#CODE 80C196NP 905#
#PM 80C196NP 905#
#CPU 80C196NU 905#
#CPU 80C296?? 905#
#PM 80C196NU 905#
Select this option for an 8-bit wide external fetch of CCB1.
#CPU 80C196NP 906#
#BIU 80C196NP 906#
#CODE 80C196NP 906#
#PM 80C196NP 906#
#CPU 80C196NU 906#
#CPU 80C296?? 906#
#PM 80C196NU 906#
Select this option for a 16-bit wide external fetch of CCB1.
#CPU 80C196NP 910#
#BIU 80C196NP 910#
#CODE 80C196NP 910#
#PM 80C196NP 910#
#CPU 80C196NP 911#
#BIU 80C196NP 911#
#CODE 80C196NP 911#
#PM 80C196NP 911#
#CPU 80C196NU 910#
#CPU 80C296?? 910#
#PM 80C196NU 910#
#CPU 80C196NU 911#
#CPU 80C296?? 911#
#PM 80C196NU 911#
Select the bus mode for an external fetch of CCB1:

Demultiplexed - data only on AD15:0
Multiplexed - address and data are multiplexed on AD15:0.
#CPU 80C196NP 915#
#BIU 80C196NP 915#
#CODE 80C196NP 915#
#PM 80C196NP 915#
#CPU 80C196NU 915#
#CPU 80C296?? 915#
#PM 80C196NU 915#
This option selects the functions of the BHE# and WR# pins to be in write-strobe mode for external bus cycles:

The BHE# pin operates as WRH#, and the WR# pin operates as WRL#.
#CPU 80C196NP 916#
#BIU 80C196NP 916#
#CODE 80C196NP 916#
#PM 80C196NP 916#
#CPU 80C196NU 916#
#CPU 80C296?? 916#
#PM 80C196NU 916#
This option selects the functions of the BHE# and WR# pins to be in standard write-control mode for external bus cycles:

The BHE# pin operates as BHE#, and the WR# pin operates as WR#.
#CPU 80C196NP 100#
#CPU 80C196NU 100#
#CPU 80C296?? 100#
#BIU 80C196?? 100#
#BIU 80C296?? 100#
#CODE 80C196?? 100#
#CODE 80C296?? 100#
#PM 80C196?? 100#
#CPU 80C196NP 101#
#CPU 80C196NU 101#
#CPU 80C296?? 101#
#BIU 80C196?? 101#
#BIU 80C296?? 101#
#CODE 80C196?? 101#
#CODE 80C296?? 101#
#PM 80C196?? 101#
#CPU 80C196NP 102#
#CPU 80C196NU 102#
#CPU 80C296?? 102#
#BIU 80C196?? 102#
#BIU 80C296?? 102#
#CODE 80C196?? 102#
#CODE 80C296?? 102#
#PM 80C196?? 102#
#CPU 80C196NP 103#
#CPU 80C196NU 103#
#CPU 80C296?? 103#
#BIU 80C196?? 103#
#BIU 80C296?? 103#
#CODE 80C196?? 103#
#CODE 80C296?? 103#
#PM 80C196?? 103#
Select the desired number of wait states.

Wait states are inserted into the bus cycle either until the READY pin is
pulled high or until this internal number is reached.
#BIU 80C196?? 104#
#BIU 80C296?? 104#
#CODE 80C196?? 104#
#CODE 80C296?? 104#
#PM 80C196?? 104#
When this option is selected, wait states are inserted into the bus cycle until
the READY pin is pulled high.
#BIU 80C196?? 502#
#BIU 80C296?? 502#
#CODE 80C196?? 502#
#CODE 80C296?? 502#
#PM 80C196?? 502#
#BIU 80C196K? 501#
#BIU 80C196N? 501#
#BIU 80C196M? 501#
#CODE 80C196K? 501#
#CODE 80C196N? 501#
#CODE 80C196M? 501#
#PM 80C196K? 501#
#PM 80C196N? 501#
#PM 80C196M? 501#
#BIU 80C196K? 500#
#BIU 80C196N? 500#
#BIU 80C196M? 500#
#CODE 80C196K? 500#
#CODE 80C196N? 500#
#CODE 80C196M? 500#
#PM 80C196K? 500#
#PM 80C196N? 500#
#PM 80C196M? 500#
Configure the system bus width.

The external bus width can be run-time configured to operate as a 16-bit
data bus or an 8-bit data bus, or the bus width can be dynamically controlled by
the BUSWIDTH pin. In dynamic mode, driving the BUSWIDTH signal low selects the
8-bit bus width and driving the BUSWIDTH signal high selects the 16-bit bus
width.
#CODE 80C196J? 501#
#BIU 80C196J? 501#
#PM 80C196J? 501#
#CODE 80C196J? 500#
#BIU 80C196J? 500#
#PM 80C196J? 500#
Configure the system bus width.

The external bus width can be run-time configured to operate as a 16-bit
data bus or an 8-bit data bus.
#BIU 80C196?? 300#
#BIU 80C296?? 300#
#CODE 80C196?? 300#
#CODE 80C296?? 300#
#PM 80C196?? 300#
#BIU 80C196?? 301#
#BIU 80C296?? 301#
#CODE 80C196?? 301#
#CODE 80C296?? 301#
#PM 80C196?? 301#
Determine whether to enable or disable the bus-hold protocol.

The device supports a bus-hold protocol that allows external devices to gain
control of the address/data bus.
#BIU 80C196?? 200#
#BIU 80C296?? 200#
#CODE 80C196?? 200#
#CODE 80C296?? 200#
#PM 80C196?? 200#
This option selects the Address Valid with Write Strobe mode.

When the Address Valid with Write Strobe mode is selected, the device
generates the ADV#, WRL#, and WRH# bus-control signals. This mode is used for
a simple system using external 16-bit RAM.
#BIU 80C196?? 201#
#BIU 80C296?? 201#
#CODE 80C196?? 201#
#CODE 80C296?? 201#
#PM 80C196?? 201#
This option selects the Address Valid Strobe mode.

When the Address Valid Strobe mode is selected, the device generates the
Address Valid (ADV#) signal instead of the Address Latch Enable (ALE) signal.
ADV# is asserted after an external address is valid.  This signal can be used
to latch the valid address and simultaneously enable an external memory
device.
#BIU 80C196?? 202#
#BIU 80C296?? 202#
#CODE 80C196?? 202#
#CODE 80C296?? 202#
#PM 80C196?? 202#
This option selects the Write Strobe mode.

The Write Strobe mode eliminates the need to externally decode high- and
low-byte writes to external 16-bit RAM in 16-bit bus mode.
#BIU 80C196?? 203#
#BIU 80C296?? 203#
#CODE 80C196?? 203#
#CODE 80C296?? 203#
#PM 80C196?? 203#
This option selects the Standard Bus mode.

The standard bus mode uses a 16-bit multiplexed address/data bus.  In this
mode, external memory is addressed through lines AD0-AD15, which form a 16-bit
multiplexed bus.  The address/data bus shares pins with ports 3 and 4.
#BIU 80C196?? 400#
#BIU 80C296?? 400#
#CODE 80C196?? 400#
#CODE 80C296?? 400#
#PM 80C196?? 400#
#BIU 80C196?? 401#
#BIU 80C296?? 401#
#CODE 80C196?? 401#
#CODE 80C296?? 401#
#PM 80C196?? 401#
#BIU 80C196?? 402#
#BIU 80C296?? 402#
#CODE 80C196?? 402#
#CODE 80C296?? 402#
#PM 80C196?? 402#
#BIU 80C196?? 403#
#BIU 80C296?? 403#
#CODE 80C196?? 403#
#CODE 80C296?? 403#
#PM 80C196?? 403#
Use this field to select a programming protection scheme for internal memory.

This device supports three protection schemes: read/write protection, write-
only protection, and read-only protection. The Chip Configuration register
controls the protection scheme.
#CPU 80C196NP 600#
#CPU 80C196NU 600#
#CPU 80C296?? 600#
#BIU 80C196?? 600#
#BIU 80C296?? 600#
#CODE 80C196?? 600#
#CODE 80C296?? 600#
#PM 80C196?? 600#
#PM 80C296?? 600#
Check this box to enable Powerdown.

When Powerdown is enabled, the IDLPD #2 instruction causes the device
to enter Powerdown mode.
#BIU 80C196?? 700#
#BIU 80C296?? 700#
#CODE 80C196?? 700#
#CODE 80C296?? 700#
#PM 80C196?? 700#
Check this box to enable the Watchdog timer.

Checking this box will enable the Watchdog timer by setting the watchdog enable
bit in the Chip Configuration 1 register; otherwise, the watchdog timer will be
enabled the first time it is cleared.
#BIU 80C196N? 800#
#CODE 80C196N? 800#
#PM 80C196N? 800#
Use this field to select the bus timing mode.

This mode is the standard mode with one wait state added to each bus cycle.
The READY signal can be used to insert additional wait states, if necessary.
#BIU 80C196N? 801#
#CODE 80C196N? 801#
#PM 80C196N? 801#
Use this field to select the bus timing mode.

This mode lengthens the read/write pulse and advances ALE to ensure that the
address will be valid when ALE goes low. This mode allows the memory device
more time to get its data onto the bus, without a wait-state penalty. This mode
is best for EPROM devices.
#BIU 80C196N? 802#
#CODE 80C196N? 802#
#PM 80C196N? 802#