Use this field to select the bus timing mode.

This mode is similar to the long read/write mode in that it, too, lengthens the
read/write pulse and advances ALE. The difference is that this mode also
places the address onto the bus earlier in the bus cycle. This mode is best for
Flash memory and SRAM devices.
#BIU 80C196N? 803#
#CODE 80C196N? 803#
#PM 80C196N? 803#
Use this field to select the bus timing mode.

Use the standard timing mode for systems that need to emulate the 8XC196KR.
#BIU 80C196N? 820#
#CODE 80C196N? 820#
#PM 80C196N? 820#
#BIU 80C196N? 821#
#CODE 80C196N? 821#
#PM 80C196N? 821#
Select between 16-bit and 24-bit addressing modes.

The 8XC196NT/NQ bonds out only 20 address lines, so only 1 Mbyte is physically
addressable.
#CPU 80C196NP 850#
#BIU 80C196N? 850#
#CODE 80C196N? 850#
#PM 80C196N? 850#
#CPU 80C196NP 851#
#BIU 80C196N? 851#
#CODE 80C196N? 851#
#PM 80C196N? 851#
Use this field to select the whether the internal OTPROM is mapped into page
FFH or both pages 00H and FFH.
#CPU 80C196NP 860#
#CPU 80C196NU 860#
#CPU 80C296?? 860#
#BIU 80C196N? 860#
#CODE 80C196N? 860#
#PM 80C196N? 860#
Check this box to enable the bus-hold protocol.

The device supports a bus-hold protocol that allows external devices to gain
control of the address/data bus.
#ICU 80C196?? 100#
#ICU 80C196?? 500#
Select the Configure option to enable or disable the individual interrupts.

The Nonmaskable, Unimplemented Opcode, and Trap interrupts are always
enabled.

Check the "Enable Global Interrupts" box to set the global interrupt bit in
the Program Status Word. This bit is set by the EI instruction and cleared by
the DI instruction.
#ICU 80C196?? 701#
#ICU 80C196?? 702#
Determine whether to enable or disable the interrupt.

Enabling an interrupt sets its corresponding bit in the interrupt mask
registers.

Disabling an interrupt clears its corresponding bit in the interrupt mask
registers.
#ICU 80C196?? 703#
Enter the name of the desired Interrupt Service Routine.
#ICU 80C196?? 501#
#ICU 80C196?? 1100#
Checking the "Enable Multiplexed Interrupts" box allows the individual
multiplexed interrupts to be enabled.

Select the configure option to enable or disable the individual multiplexed
interrupts.  Unless the "Enable Multiplexed Interrupts" box is checked, the
individual multiplexed interrupts will NOT be enabled, regardless of their
configurations.
#ICU 80C296?? 302#
#ICU 80C296?? 200#
#ICU 80C296?? 201#
#ICU 80C296?? 203#
#ICU 80C296?? 204#
#ICU 80C296?? 205#
#ICU 80C296?? 206#
#ICU 80C296?? 207#
#ICU 80C296?? 208#
#ICU 80C296?? 209#
#ICU 80C296?? 210#
#ICU 80C296?? 211#
#ICU 80C296?? 212#
#ICU 80C296?? 213#
#ICU 80C296?? 214#
Select the Configure option to enable or disable the individual interrupts.

The Nonmaskable, Unimplemented Opcode, and Trap interrupts are always
enabled.

Check the "Enable Global Interrupts" box to set the global interrupt bit in
the Program Status Word. This bit is set by the EI instruction and cleared by
the DI instruction.
#ICU 80C296?? 220#
#ICU 80C296?? 221#
#ICU 80C296?? 223#
#ICU 80C296?? 224#
#ICU 80C296?? 225#
#ICU 80C296?? 226#
#ICU 80C296?? 227#
#ICU 80C296?? 228#
#ICU 80C296?? 229#
#ICU 80C296?? 230#
#ICU 80C296?? 231#
#ICU 80C296?? 232#
#ICU 80C296?? 233#
#ICU 80C296?? 234#
Selecting this button yeilds a dialog allowing you to route this interrupt
source to a priority/vector.
#ICU 80C296?? 243#
#ICU 80C296?? 244#
#ICU 80C296?? 245#
#ICU 80C296?? 246#
This button toggles between 4 states.  Each state represents the input triggering
method used for this interrupt source input pin.
The interrupt source can be +/-level or +/-edge triggered.
#ICU 80C296?? 300#
Check this to enable the programmable interrupt priorities and vectors.
#ICU 80C296?? 301#
This register defines the base address for the interrupts.
#Serial 80C196?? 103#
#Serial 80C296?? 103#
Selecting this option enables a divide by 2 prescaler for the baud rate generator.

This option is only available when the internal clock source is used.
#Serial 80C296?? 700#
#PM 80C296?? 700#
Selecting this option disables the serial baud rate generator/counter.
This is done to conserve power usage.
#Serial 80C196?? 100#
#Serial 80C296?? 100#
Select this option to enable the Transmit interrupt.

During a serial transmission, the TI flag is set at the beginning of the stop
bit.  When the TI flag is set, a pending transmit interrupt occurs.  If the
interrupt is enabled, the interrupt signal is generated.
#Serial 80C196?? 101#
#Serial 80C296?? 101#
Select this option to enable the Receive interrupt.

During a serial reception in Modes 0, 1, and 3, the RI flag is set just after
the end of the stop bit.  When the RI flag is set, a pending receive interrupt
occurs.  If the interrupt is enabled, the interrupt signal is generated.

In Mode 2, the receive interrupt is generated only if the ninth data bit is
set.
#Serial 80C196?? 202#
#Serial 80C296?? 202#
#Serial 80C196?? 203#
#Serial 80C296?? 203#
Determine the value of the 9th data bit.

Operations in Modes 2 and 3 use data frames consisting of 11 bits: one start
bit, 9 data bits, and one stop bit.  When parity is enabled in Mode 3, the
ninth data bit becomes the even parity bit.

When parity is disabled in Modes 2 and 3, the desired value of the ninth data
bit is written to the TB8 (transmit bit eight) bit in the Serial Port Control
Register.  During a reception, the ninth data bit is read in the Serial Port
Status Register.

In Mode 2, during a reception, the RI flag is set and an interrupt is generated
only if the ninth data bit is set.
#Serial 80C196?? 300#
#Serial 80C296?? 300#
This option selects an internal clock source for the baud-rate generator.

When an internal clock source is selected, the XTAL1 input signal (Fosc)
becomes the clock input to the baud-rate generator.
#Serial 80C196?? 500#
#Serial 80C296?? 500#
Select the desired baud rate for all serial I/O modes.

Maximum Baud Rate:
Mode  Internal Clock External Clock
0  Fosc / 2    T2CLK frequency
1, 2, 3  Fosc / 16      T2CLK frequency / 8
#Serial 80C196?? 501#
#Serial 80C296?? 501#
Select this option to enable the RXD pin.

In Modes 1, 2, and 3, RXD is used to receive serial port data.  In Mode 0, it
functions as an input or an open-drain output for data.
#Serial 80C196?? 502#
#Serial 80C296?? 502#
Select this option to enable the TXD pin.

In Modes 1, 2, and 3, TXD is used to transmit serial port data.  In Mode 0, it
is used as the serial clock output.
#Serial 80C196?? 600#
#Serial 80C296?? 600#
This option selects the Synchronous 8-bit Serial Mode.

In this mode, the TXD pin outputs a set of eight clock pulses, while the RXD
pin either transmits or receives data.  Data is transferred eight bits at a
time, with the least-significant bit first.
#Serial 80C196?? 601#
#Serial 80C296?? 601#
This option selects the Asynchronous 8-bit Serial Mode.

Mode 1 is the standard 8-bit, asynchronous mode used for normal serial
communications.  Modes 1, 2, and 3 are full-duplex serial transmit/receive
modes, meaning that they can transmit and receive data simultaneously.
#Serial 80C196?? 602#
#Serial 80C296?? 602#
This option selects the Asynchronous Ninth-bit Recognition Serial Mode.

Mode 2 is a 9-bit asynchronous mode typically used for interprocessor
communications.  Modes 1, 2, and 3 are full-duplex serial transmit/receive
modes, meaning that they can transmit and receive data simultaneously.  In
this mode, a serial reception generates an interrupt only if the ninth data
bit is set.  The Mode 2 data frame consists of a start bit (0), nine data bits
(LSB first), and a stop bit (1).  Parity cannot be enabled in this mode.
#Serial 80C196?? 603#
#Serial 80C296?? 603#
This option selects the Asynchronous 9-bit Serial Mode.

The Mode 3 data frame consists of a start bit (0), nine data bits (LSB first),
and a stop bit (1).  Modes 1, 2, and 3 are full-duplex serial transmit/receive
modes, meaning that they can transmit and receive data simultaneously. In Mode
3, the serial port always generates an interrupt upon completion of a data
transmission or reception.  If parity is enabled, the ninth data bit becomes
the even parity bit.
#Serial 80C196?? 301#
#Serial 80C296?? 301#
This option selects an external clock source for the baud-rate generator.

When an external clock source is selected, the external signal on the T1CLK pin
becomes the clock input into the baud-rate generator.  The maximum T1CLK input
frequency is Fosc/4.
#Serial 80C196J? 200#
#Serial 80C196KR 200#
#Serial 80C196KQ 200#
#Serial 80C196KT 200#
#Serial 80C196N? 200#
Select this option to enable parity (Modes 1 and 3 only).

Mode 1 - If parity is enabled, an even parity bit is sent instead of the eighth data
bit, and parity is checked on reception.

Mode 3 - If parity is enabled, an even parity bit is sent instead of the ninth data
bit and the Serial Port Status Register contains a Receive Parity Error bit.
#Serial 80C196N? 204#
#Serial 80C196KT 204#
#Serial 80C196N? 205#
#Serial 80C196KT 205#
Select even or odd parity (Modes 1 and 3 only).

Mode 1 - If parity is enabled, a parity bit is sent instead of the eighth data
bit, and parity is checked on reception.

Mode 3 - If parity is enabled, a parity bit is sent instead of the ninth data
bit and the Serial Port Status Register contains a Receive Parity Error bit.
#PTS 80C196?? 102#
#PTS 80C196?? 400#
The Configure option allows you to select the PTS mode for each interrupt.

Check the "Enable PTS" box to set the PTS enable bit in the Program Status
Word.  This bit is set by the EPTS instruction and cleared by the DPTS
instruction.

Warning:  If the PTS receives an interrupt request from one of the multiplexed
interrupt sources (EPAx, CMP0,1, TMR 1,2) it cannot determine which source
actually generated the interrupt.
#PTS 80C196?? 602#
Select this option to enable the auto-increment and update features
for the destination address.

The auto-increment feature causes the PTS to increment the address
at the end of each transfer, and the update feature causes the PTSDST
register to retain its final address value.
#PTS 80C196?? 603#
Select this option to enable the auto-increment and update features
for the source address.

The auto-increment feature causes the PTS to increment the address
at the end of each transfer, and the update feature causes the PTSSRC
register to retain its final address value.
#PTS 80C196?? 652#
Select this option to enable the auto-increment destination address feature.

This feature causes the PTS to increment the destination address at the end of
each PTS transfer.
#PTS 80C196?? 653#
Select this option to enable the auto-increment source address feature.

This feature causes the PTS to increment the source address at the end of each
PTS cycle.
#PTS 80C196?? 604#
Enter the PTS destination address.

In single transfer mode, the PTS moves a byte or word from the location pointed 
to by the PTS source register to the location pointed to by the PTS destination
register.
#PTS 80C196?? 650#
Enter the PTS destination address.

In block transfer mode, the PTS moves a block of bytes or words from the
location pointed to by the PTS source register to the location pointed to by
the PTS destination register.
#PTS 80C196?? 605#
#PTS 80C196?? 654#
#PTS 80C196?? 700#
#PTS 80C196?? 902#
#PTS 80C196?? 1003#
Select this option to enable the PTS interrupt.

Enabling the PTS interrupt causes the associated bits in the Interrupt Mask
registers and the PTS Select register to be set.
#PTS 80C196?? 606#
#PTS 80C196?? 655#
#PTS 80C196?? 701#
Enter the desired number of PTS cycles.

The number of cycles should be a number from 1 to 256. The PTS decrements the
count before each cycle; therefore, an entry of 0 would cause the PTS to perform
256 cycles.
#PTS 80C196?? 607#
Enter the PTS source address.

In single transfer mode, the PTS moves a byte or word from the location pointed 
to by the PTS source register to the location pointed to by the PTS destination
register.
#PTS 80C196?? 651#
Enter the PTS source address.

In block transfer mode, the PTS moves a block of bytes or words from the
location pointed to by the PTS source register to the location pointed to by
the PTS destination register.
#PTS 80C196?? 608#
#PTS 80C196?? 609#
#PTS 80C196?? 657#
#PTS 80C196?? 658#
Determine whether to transfer bytes or words.
#PTS 80C196?? 659#
Select this option to enable the update destination address feature.

This feature causes the PTSDST register to retain its final value at the end
of a PTS cycle. Otherwise, the register reverts to the value that existed at
the beginning of the PTS cycle.
#PTS 80C196?? 660#
Select this option to enable the update source address feature.

This feature causes the PTSSRC register to retain its final value at the end
of a PTS cycle. Otherwise, the register reverts to the value that existed at
the beginning of the PTS cycle.
#PTS 80C196?? 656#
Enter the desired number of bytes or words to be transferred in each block.

The number of transfers must be a number from 1-32.
#PTS 80C196?? 702#
Select this option to enable the update feature.

When this feature is enabled, the register that points to the
table of conversion commands and results (PTS_S/D) retains its final value.

When this feature is disabled, the PTS_S/D register reverts to the value that
existed at the beginning of the PTS cycle.
#PTS 80C196?? 703#
Enter the name of the table of A/D conversion commands and results.
#PTS 80C196?? 900#
Enter a constant in this field.

When the PTS interrupt occurs, this constant will be added to the value pointed 
to by the PTS Pointer.
#PTS 80C196?? 1000#
Enter a constant in this field.

If the toggle bit is 0 when the PTS interrupt occurs, this constant will be
added to the value pointed to by the PTS Pointer.
#PTS 80C196?? 1002#
Enter a constant in this field.

If the toggle bit is 1 when the PTS interrupt occurs, this constant will be
added to the value pointed to by the PTS Pointer.
#PTS 80C196?? 1001#
Enter the address of a memory location.

When the PTS interrupt occurs, CONST1 or CONST2 (depending on the value of the
toggle bit) will be added to the value pointed to by the PTS Pointer.

If the toggle bit is 0, CONST1 will be added to the value pointed to by the PTS
Pointer.

If the toggle bit is 1, CONST2 will be added to the value pointed to by the PTS
Pointer.
#PTS 80C196?? 901#
Enter the address of a memory location.

When the PTS interrupt occurs, CONST1 will be added to the value pointed to by
the PTS Pointer.
#PTS 80C196?? 903#
#PTS 80C196?? 904#
#PTS 80C196?? 1004#
#PTS 80C196?? 1005#
Use this field to select the initial value of the toggle bit.

This bit is toggled at the end of each PTS cycle.
#EPA? 80C196?? 200#
#EPA? 80C296?? 200#
#EPA? 80C196?? 201#
#EPA? 80C296?? 201#
#EPA? 80C196?? 202#
#EPA? 80C296?? 202#
#EPA? 80C196?? 203#
#EPA? 80C296?? 203#
Select the type of event you want this EPA module to capture.

When the event occurs, the value of the Compare timer will be written to the EPA
event-time register.
#Comp? 80C196?? 240#
#Comp? 80C296?? 240#
#Comp? 80C196?? 241#
#Comp? 80C296?? 241#
#Comp? 80C196?? 242#
#Comp? 80C296?? 242#
#Comp? 80C196?? 243#