Check this box to enable the Slave Port Output Buffer Empty interrupt.
#SlvPrt 80C196?? 123#
#SlvPrt 80C296?? 123#
Check this box to enable Slave Port operation.
#SlvPrt 80C196?? 105#
#SlvPrt 80C296?? 105#
Select the Slave Port operating mode.

The standard mode supports either a demultiplexed or a multiplexed bus
and uses the Command Buffer Full interrupt.
#SlvPrt 80C196?? 106#
#SlvPrt 80C296?? 106#
Select the Slave Port operating mode.

The shared memory mode supports only a multiplexed bus
and uses the Input Buffer Full and Output Buffer Empty interrupts.
#Sync? 80C196?? 210#
#Sync? 80C296?? 210#
#Sync? 80C196?? 211#
#Sync? 80C296?? 211#
#Sync? 80C196?? 212#
#Sync? 80C296?? 212#
#Sync? 80C196?? 213#
#Sync? 80C296?? 213#
Select the SSIO channel configuration.

This SSIO channel can be configured as the master transmitter, slave
transmitter, master receiver, or slave receiver.
#Sync? 80C196?? 220#
#Sync? 80C296?? 220#
Check this box to enable the transmitter/receiver toggle.

Enabling this feature allows the channel configuration to change immediately
on transfer completions, thus avoiding possible contention on the data line.
#Sync? 80C196?? 225#
#Sync? 80C296?? 225#
Check this box to enable transceiver handshaking.

When handshaking is enabled, the slave pulls its clock input (SCx) low
whenever it is busy, and the master leaves its clock output (SCx) high at the
end of each byte transfer.
#Sync? 80C196?? 230#
#Sync? 80C296?? 230#
Check this box to enable single transfer.

Enabling single transfer allows reception or transmission of one byte.
Single transfer must be enabled for handshaking modes.
#Sync? 80C196?? 235#
#Sync? 80C296?? 235#
Select this option to configure this SSIO channel for automatic transfer
re-enable.

This mode automatically enables the reception or transmission of any bytes at
the end of a transfer. This mode must be enabled for handshaking modes.
#Sync? 80C196?? 301#
#Sync? 80C296?? 301#
This option selects an internal clock source for the baud-rate generator.

When an internal clock source is selected, the XTAL1 input signal (Fosc)
becomes the clock input into the baud-rate generator.
#Sync? 80C196?? 300#
#Sync? 80C296?? 300#
This option selects an external clock source for the baud-rate generator.

When an external clock source is selected, the external signal on the T2CLK pin
becomes the clock input into the baud-rate generator.  The maximum T2CLK input
frequency is Fosc/4.
#Sync? 80C196?? 320#
#Sync? 80C296?? 320#
Enter the baud rate value in kHz.

Valid baud rate values range from Fosc/8 to Fosc/1024.
#Sync? 80C196?? 400#
#Sync? 80C296?? 400#
Check this box to enable the SSIO interrupt.

The SSIO can generate a transfer interrupt.
#Timer? 80C196?? 170#
#Timer? 80C296?? 170#
Select the timer mode.

The first item is the timer clock source and the second item is the timer
direction source.

If quadrature clocking is used, the TxDIR and TxCLK pins must be configured as input pins.
#Timer? 80C196?? 110#
#Timer? 80C296?? 110#
Select a timer prescale value.
#Timer? 80C196?? 121#
#Timer? 80C296?? 121#
Select this option to configure the timer for up counting.
#Timer? 80C196?? 122#
#Timer? 80C296?? 122#
Select this option to configure the timer for down counting.
#Timer? 80C196?? 130#
#Timer? 80C296?? 130#
Check this box to enable the timer.
#Timer? 80C196?? 131#
#Timer? 80C296?? 131#
Check this box to enable the Timer Overflow/Underflow interrupt.

Both Timer 1 and Timer 2 can generate the Timer Overflow/Underflow interrupt.
The EPA_PEND1 register can be read to determine which timer generated the
interrupt.
#WDT 80C196?? 100#
#WDT 80C296?? 100#
The Watchdog register must be cleared within every 64K state times to hold off
a Watchdog Timer reset.
#AD 80C196?? 30022#
#AD 80C296?? 30022#
#Serial 80C196?? 30022#
#Serial 80C296?? 30022#
#Sync? 80C196?? 30022#
#Sync? 80C296?? 30022#
Enter the appropriate frequency in MHz.
#CSU 80C196NP 100#
#CSU 80C196NU 100#
#CSU 80C296?? 100#
Select the block size (in bytes) for the address range assigned to CS0#.
#CSU 80C196NP 200#
#CSU 80C196NU 200#
#CSU 80C296?? 200#
Select the block size (in bytes) for the address range assigned to CS1#.
#CSU 80C196NP 300#
#CSU 80C196NU 300#
#CSU 80C296?? 300#
Select the block size (in bytes) for the address range assigned to CS2#.
#CSU 80C196NP 400#
#CSU 80C196NU 400#
#CSU 80C296?? 400#
Select the block size (in bytes) for the address range assigned to CS3#.
#CSU 80C196NP 500#
#CSU 80C196NU 500#
#CSU 80C296?? 500#
Select the block size (in bytes) for the address range assigned to CS4#.
#CSU 80C196NP 600#
#CSU 80C196NU 600#
#CSU 80C296?? 600#
Select the block size (in bytes) for the address range assigned to CS5#.
#CSU 80C196NP 101#
#CSU 80C196NU 101#
#CSU 80C296?? 101#
Enter the start address for the address range assigned to CS0#.  The start address for a 2^n-byte address block must be on a 2^n-byte boundary (that is, the start address must be evenly divisible by the block size).
#CSU 80C196NP 201#
#CSU 80C196NU 201#
#CSU 80C296?? 201#
Enter the start address for the address range assigned to CS1#.  The start address for a 2^n-byte address block must be on a 2^n-byte boundary (that is, the start address must be evenly divisible by the block size).
#CSU 80C196NP 301#
#CSU 80C196NU 301#
#CSU 80C296?? 301#
Enter the start address for the address range assigned to CS2#.  The start address for a 2^n-byte address block must be on a 2^n-byte boundary (that is, the start address must be evenly divisible by the block size).
#CSU 80C196NP 401#
#CSU 80C196NU 401#
#CSU 80C296?? 401#
Enter the start address for the address range assigned to CS3#.  The start address for a 2^n-byte address block must be on a 2^n-byte boundary (that is, the start address must be evenly divisible by the block size).
#CSU 80C196NP 501#
#CSU 80C196NU 501#
#CSU 80C296?? 501#
Enter the start address for the address range assigned to CS4#.  The start address for a 2^n-byte address block must be on a 2^n-byte boundary (that is, the start address must be evenly divisible by the block size).
#CSU 80C196NP 601#
#CSU 80C196NU 601#
#CSU 80C296?? 601#
Enter the start address for the address range assigned to CS5#.  The start address for a 2^n-byte address block must be on a 2^n-byte boundary (that is, the start address must be evenly divisible by the block size).
#CSU 80C196NP 102#
#CSU 80C196NU 102#
#CSU 80C296?? 102#
This button controls the address/data multiplexing on the external bus for the address range assigned to CS0#.  Select this button for address and data on AD15:0.
#CSU 80C196NP 202#
#CSU 80C196NU 202#
#CSU 80C296?? 202#
This button controls the address/data multiplexing on the external bus for the address range assigned to CS1#.  Select this button for address and data on AD15:0.
#CSU 80C196NP 302#
#CSU 80C196NU 302#
#CSU 80C296?? 302#
This button controls the address/data multiplexing on the external bus for the address range assigned to CS2#.  Select this button for address and data on AD15:0.
#CSU 80C196NP 402#
#CSU 80C196NU 402#
#CSU 80C296?? 402#
This button controls the address/data multiplexing on the external bus for the address range assigned to CS3#.  Select this button for address and data on AD15:0.
#CSU 80C196NP 502#
#CSU 80C196NU 502#
#CSU 80C296?? 502#
This button controls the address/data multiplexing on the external bus for the address range assigned to CS4#.  Select this button for address and data on AD15:0.
#CSU 80C196NP 602#
#CSU 80C196NU 602#
#CSU 80C296?? 602#
This button controls the address/data multiplexing on the external bus for the address range assigned to CS5#.  Select this button for address and data on AD15:0.
#CSU 80C196NP 103#
#CSU 80C196NU 103#
#CSU 80C296?? 103#
This button controls the address/data multiplexing on the external bus for the address range assigned to CS0#.  Select this button for data only on AD15:0.
#CSU 80C196NP 203#
#CSU 80C196NU 203#
#CSU 80C296?? 203#
This button controls the address/data multiplexing on the external bus for the address range assigned to CS1#.  Select this button for data only on AD15:0.
#CSU 80C196NP 303#
#CSU 80C196NU 303#
#CSU 80C296?? 303#
This button controls the address/data multiplexing on the external bus for the address range assigned to CS2#.  Select this button for data only on AD15:0.
#CSU 80C196NP 403#
#CSU 80C196NU 403#
#CSU 80C296?? 403#
This button controls the address/data multiplexing on the external bus for the address range assigned to CS3#.  Select this button for data only on AD15:0.
#CSU 80C196NP 503#
#CSU 80C196NU 503#
#CSU 80C296?? 503#
This button controls the address/data multiplexing on the external bus for the address range assigned to CS4#.  Select this button for data only on AD15:0.
#CSU 80C196NP 603#
#CSU 80C196NU 603#
#CSU 80C296?? 603#
This button controls the address/data multiplexing on the external bus for the address range assigned to CS5#.  Select this button for data only on AD15:0.
#CSU 80C196NP 104#
#CSU 80C196NU 104#
#CSU 80C296?? 104#
This button controls the bus width for the address range assigned to CS0#.  Select this button for a 16-bit bus.
#CSU 80C196NP 204#
#CSU 80C196NU 204#
#CSU 80C296?? 204#
This button controls the bus width for the address range assigned to CS1#.  Select this button for a 16-bit bus.
#CSU 80C196NP 304#
#CSU 80C196NU 304#
#CSU 80C296?? 304#
This button controls the bus width for the address range assigned to CS2#.  Select this button for a 16-bit bus.
#CSU 80C196NP 404#
#CSU 80C196NU 404#
#CSU 80C296?? 404#
This button controls the bus width for the address range assigned to CS3#.  Select this button for a 16-bit bus.
#CSU 80C196NP 504#
#CSU 80C196NU 504#
#CSU 80C296?? 504#
This button controls the bus width for the address range assigned to CS4#.  Select this button for a 16-bit bus.
#CSU 80C196NP 604#
#CSU 80C196NU 604#
#CSU 80C296?? 604#
This button controls the bus width for the address range assigned to CS5#.  Select this button for a 16-bit bus.
#CSU 80C196NP 105#
#CSU 80C196NU 105#
#CSU 80C296?? 105#
This button controls the bus width for the address range assigned to CS0#.  Select this button for a 8-bit bus.
#CSU 80C196NP 205#
#CSU 80C196NU 205#
#CSU 80C296?? 205#
This button controls the bus width for the address range assigned to CS1#.  Select this button for a 8-bit bus.
#CSU 80C196NP 305#
#CSU 80C196NU 305#
#CSU 80C296?? 305#
This button controls the bus width for the address range assigned to CS2#.  Select this button for a 8-bit bus.
#CSU 80C196NP 405#
#CSU 80C196NU 405#
#CSU 80C296?? 405#
This button controls the bus width for the address range assigned to CS3#.  Select this button for a 8-bit bus.
#CSU 80C196NP 505#
#CSU 80C196NU 505#
#CSU 80C296?? 505#
This button controls the bus width for the address range assigned to CS4#.  Select this button for a 8-bit bus.
#CSU 80C196NP 605#
#CSU 80C196NU 605#
#CSU 80C296?? 605#
This button controls the bus width for the address range assigned to CS5#.  Select this button for a 8-bit bus.
#CSU 80C196NP 106#
#CSU 80C196NU 106#
#CSU 80C296?? 106#
Select the number of wait states that are inserted into external bus cycles for the address range assigned to CS0#.  An external device can request additional wait states via the READY signal.
#CSU 80C196NP 206#
#CSU 80C196NU 206#
#CSU 80C296?? 206#
Select the number of wait states that are inserted into external bus cycles for the address range assigned to CS1#.  An external device can request additional wait states via the READY signal.
#CSU 80C196NP 306#
#CSU 80C196NU 306#
#CSU 80C296?? 306#
Select the number of wait states that are inserted into external bus cycles for the address range assigned to CS2#.  An external device can request additional wait states via the READY signal.
#CSU 80C196NP 406#
#CSU 80C196NU 406#
#CSU 80C296?? 406#
Select the number of wait states that are inserted into external bus cycles for the address range assigned to CS3#.  An external device can request additional wait states via the READY signal.
#CSU 80C196NP 506#
#CSU 80C196NU 506#
#CSU 80C296?? 506#
Select the number of wait states that are inserted into external bus cycles for the address range assigned to CS4#.  An external device can request additional wait states via the READY signal.
#CSU 80C196NP 606#
#CSU 80C196NU 606#
#CSU 80C296?? 606#
Select the number of wait states that are inserted into external bus cycles for the address range assigned to CS5#.  An external device can request additional wait states via the READY signal.
#CSU 80C196NP 107#
#CSU 80C196NU 107#
#CSU 80C296?? 107#
Check this box to enable the CS0# signal (special function) on the port pin.
#CSU 80C196NP 207#
#CSU 80C196NU 207#
#CSU 80C296?? 207#
Check this box to enable the CS1# signal (special function) on the port pin.
#CSU 80C196NP 307#
#CSU 80C196NU 307#
#CSU 80C296?? 307#
Check this box to enable the CS2# signal (special function) on the port pin.
#CSU 80C196NP 407#
#CSU 80C196NU 407#
#CSU 80C296?? 407#
Check this box to enable the CS3# signal (special function) on the port pin.
#CSU 80C196NP 507#
#CSU 80C196NU 507#
#CSU 80C296?? 507#
Check this box to enable the CS4# signal (special function) on the port pin.
#CSU 80C196NP 607#
#CSU 80C196NU 607#
#CSU 80C296?? 607#
Check this box to enable the CS5# signal (special function) on the port pin.
#CSU 80C296?? 710#
#CSU 80C296?? 711#
#CSU 80C296?? 712#
#CSU 80C296?? 713#
#CSU 80C296?? 714#
#CSU 80C296?? 715#
Check this box to enable the Remapping feature for this Chip Select.
#CSU 80C296?? 700#
#CSU 80C296?? 701#
#CSU 80C296?? 702#
#CSU 80C296?? 703#
#CSU 80C296?? 705#
#CSU 80C296?? 704#
Check this box to add an additional state time to each write operation for this CS.
#PWM0 80C196NP 100#
#PWM1 80C196NP 100#
#PWM2 80C196NP 100#
#PWM0 80C196NU 100#
#PWM0 80C296?? 100#
#PWM1 80C196NU 100#
#PWM1 80C296?? 100#
#PWM2 80C196NU 100#
#PWM2 80C296?? 100#
Select this option for a PWM period of 256 state times.
#PWM0 80C196NP 101#
#PWM1 80C196NP 101#
#PWM2 80C196NP 101#
#PWM0 80C196NU 101#
#PWM0 80C296?? 101#
#PWM1 80C196NU 101#
#PWM1 80C296?? 101#
#PWM2 80C196NU 101#
#PWM2 80C296?? 101#
Select this option for a PWM period of 512 state times.
#PWM0 80C196NU 104#
#PWM0 80C296?? 104#
#PWM1 80C196NU 104#
#PWM1 80C296?? 104#
#PWM2 80C196NU 104#
#PWM2 80C296?? 104#
Select this option for a PWM period of 1024 state times.
#PWM0 80C196NP 200#
#PWM1 80C196NP 201#
#PWM2 80C196NP 202#
#PWM0 80C196NU 200#
#PWM0 80C296?? 200#
#PWM1 80C196NU 201#
#PWM1 80C296?? 201#
#PWM2 80C196NU 202#
#PWM2 80C296?? 202#
Select this option to enable the PWM output.

Selecting the PWM output function disables the port function.
#PWM0 80C196NP 300#
#PWM1 80C196NP 301#
#PWM2 80C196NP 302#
#PWM0 80C196NU 300#
#PWM0 80C296?? 300#
#PWM1 80C196NU 301#
#PWM1 80C296?? 301#
#PWM2 80C196NU 302#
#PWM2 80C296?? 302#
Enter the PWM duty cycle percentage.

Entering a value in this field also updates the Control Register field. The
PWM control register equals 256 * (duty cycle%).
#PWM0 80C296?? 672#
#PWM1 80C296?? 672#
#PWM2 80C296?? 672#
#PM 80C296?? 672#
Setting this bit will disable the PWM duty cycle counter to reduce power
consumption when not being used.  This disables all PWM generation.
#PWM0 80C196NP 400#
#PWM0 80C196NU 400#
#PWM0 80C296?? 400#
Enter a value between 0 and 255.

The PWM0 Control Register, in conjunction with the PWM prescaler, determines
how long the PWM output is held high during the pulse, effectively controlling
the duty cycle.  The value written to the PWM0 Control Register can be from 0
to 255 state times (0% to 99.6% duty cycle).

Entering a value in this field also updates the Duty Cycle field. The duty cycle
equals (PWM Control Register) / 256.
#PWM1 80C196NP 401#
#PWM1 80C196NU 401#
#PWM1 80C296?? 401#
Enter a value between 0 and 255.

The PWM1 Control Register, in conjunction with the PWM prescaler, determines
how long the PWM output is held high during the pulse, effectively controlling
the duty cycle.  The value written to the PWM1 Control Register can be from 0
to 255 state times (0% to 99.6% duty cycle).

Entering a value in this field also updates the Duty Cycle field. The duty cycle
equals (PWM Control Register) / 256.
#PWM2 80C196NP 402#
#PWM2 80C196NU 402#
#PWM2 80C296?? 402#
Enter a value between 0 and 255.

The PWM2 Control Register, in conjunction with the PWM prescaler, determines
how long the PWM output is held high during the pulse, effectively controlling
the duty cycle.  The value written to the PWM2 Control Register can be from 0
to 255 state times (0% to 99.6% duty cycle).

Entering a value in this field also updates the Duty Cycle field. The duty cycle
equals (PWM Control Register) / 256.
#