/*
 *  Copyright (c) 1995, Intel Corporation
 *
 *  $Workfile:   196c.cod  $
 *  $Revision:   1.1  $
 *  $Modtime:   Mar 22 1995 16:58:12  $
 *
 *  Purpose:
 *
 *
 *
 *
 *
 *  Compiler:       
 *
 *  Ext Packages:   
 *
 * 
 *
 */
196KD/KC/KB 198/184
##80C196K? WRITE# 500
##80C19? WRITE# 500
$$IFSTR$ REG_MNEM "CCR" |STR "BAUD_RATE" |STR "WATCHDOG" |STR "IOPORT0"
  $$IFSTR$ REG_MNEM "CCR"
#pragma CCB(0x$%XREG_VALUE & 0x0FF$)
  $$END$
  $$IFSTR$ REG_MNEM "BAUD_RATE"
wsr = $%cWSR_WRITE$;
@@REG_MNEM@ = $%cREG_VALUE & 0xff$;
@@REG_MNEM@ = $%cREG_VALUE > 8$;
  $$END$
  $$IFSTR$ REG_MNEM "WATCHDOG"
wsr = $%cWSR_WRITE$;
@@REG_MNEM@ = 0x1E;
@@REG_MNEM@ = 0xE1;
  $$END$
  $$IFSTR$ REG_MNEM "IOPORT0"
Unsupported Operation:
@@REG_MNEM@ register is a read-only register.
  $$END$
$$END$
$$ELSE$
  $$IF$ REG_USEMACRO
_WriteSFR(@@REG_MNEM@,$%cREG_VALUE$);
  $$END$
  $$ELSE$
    $$IFN$ REG_WSRALL
wsr = $%cWSR_WRITE$;
   $$END$
@@REG_MNEM@ = $%cREG_VALUE$;
  $$END$
$$END$
##80C196K? READ# 500
##80C19? READ# 500
$$IFSTR$ REG_MNEM "CCR" |STR "BAUD_RATE" |STR "WATCHDOG"
  $$IFSTR$ REG_MNEM "CCR"
const unsigned short %s = $%cREG_VALUE$;
#pragma Locate(%s=0x2018)
  $$END$
  $$IFSTR$ REG_MNEM "BAUD_RATE"
Unsupported Operation:
  @@REG_MNEM@ register is a write-only register.
  $$END$
  $$IFSTR$ REG_MNEM "WATCHDOG"
Unsupported Operation:
@@REG_MNEM@ register is a write-only register.
  $$END$
$$END$
$$ELSE$
  $$IF$ REG_USEMACRO
_ReadSFR(UserVar,@@REG_MNEM@);
  $$END$
  $$ELSE$
    $$IFN$ REG_WSRALL
wsr = $%cWSR_READ$;
    $$END$
UserVar = @@REG_MNEM@;
  $$END$
$$END$
##80C196K? OR# 500
##80C19? OR# 500
$$IFSTR$ REG_MNEM "CCR" |STR "BAUD_RATE" |STR "WATCHDOG" |STR "IOPORT0"
  $$IFSTR$ REG_MNEM "CCR"
Unsupported Operation:
@@REG_MNEM@ register is a read-only register.
  $$END$
  $$IFSTR$ REG_MNEM "BAUD_RATE"
Unsupported Operation:
@@REG_MNEM@ register is a write-only register.
  $$END$
  $$IFSTR$ REG_MNEM "WATCHDOG"
Unsupported Operation:
@@REG_MNEM@ register is a write-only register.
  $$END$
  $$IFSTR$ REG_MNEM "IOPORT0"
Unsupported Operation:
@@REG_MNEM@ register is a read-only register.
  $$END$
$$END$
$$ELSE$
  $$IF$ REG_USEMACRO
_OrSFR(@@REG_MNEM@,$%cREG_VALUE$);
  $$END$
  $$ELSE$
    $$IFN$ REG_WSRALL
wsr = $%cWSR_READ$;
    $$END$
    $$IF$ REG_WSRSAME || REG_WSRALL
@@REG_MNEM@ |= $%cREG_VALUE$;
    $$END$
    $$IFN$ REG_WSRSAME &! REG_WSRALL
UserVar = @@REG_MNEM@;
wsr = $%cWSR_WRITE$;
@@REG_MNEM@ = UserVar | $%cREG_VALUE$;
    $$END$
  $$END$
$$END$
##80C196K? AND# 500
##80C19? AND# 500
$$IFSTR$ REG_MNEM "CCR" |STR "BAUD_RATE" |STR "WATCHDOG" |STR "IOPORT0"
  $$IFSTR$ REG_MNEM "CCR"
Unsupported Operation:
@@REG_MNEM@ register is a read-only register.
  $$END$
  $$IFSTR$ REG_MNEM "BAUD_RATE"
Unsupported Operation:
@@REG_MNEM@ register is a write-only register.
  $$END$
  $$IFSTR$ REG_MNEM "WATCHDOG"
Unsupported Operation:
@@REG_MNEM@ register is a write-only register.
  $$END$
  $$IFSTR$ REG_MNEM "IOPORT0"
Unsupported Operation:
@@REG_MNEM@ register is a read-only register.
  $$END$
$$END$
$$ELSE$
  $$IF$ REG_USEMACRO
_AndSFR(@@REG_MNEM@,$%cREG_VALUE$);
  $$END$
  $$ELSE$
    $$IFN$ REG_WSRALL
wsr = $%cWSR_READ$;
    $$END$
    $$IF$ REG_WSRSAME || REG_WSRALL
@@REG_MNEM@ &= $%cREG_VALUE$;
    $$END$
    $$IFN$ REG_WSRSAME &! REG_WSRALL
UserVar = @@REG_MNEM@;
wsr = $%cWSR_WRITE$;
@@REG_MNEM@ = UserVar & $%cREG_VALUE$;
    $$END$
  $$END$
$$END$
##80C196K? XOR# 500
##80C19? XOR# 500
$$IFSTR$ REG_MNEM "CCR" |STR "BAUD_RATE" |STR "WATCHDOG" |STR "IOPORT0"
  $$IFSTR$ REG_MNEM "CCR"
Unsupported Operation:
@@REG_MNEM@ register is a read-only register.
  $$END$
  $$IFSTR$ REG_MNEM "BAUD_RATE"
Unsupported Operation:
@@REG_MNEM@ register is a write-only register.
  $$END$
  $$IFSTR$ REG_MNEM "WATCHDOG"
Unsupported Operation:
@@REG_MNEM@ register is a write-only register.
  $$END$
  $$IFSTR$ REG_MNEM "IOPORT0"
Unsupported Operation:
@@REG_MNEM@ register is a read-only register.
  $$END$
$$END$
$$ELSE$
  $$IF$ REG_USEMACRO
_XorSFR(@@REG_MNEM@,$%cREG_VALUE$);
  $$END$
  $$ELSE$
    $$IFN$ REG_WSRALL
wsr = $%cWSR_READ$;
    $$END$
    $$IF$ REG_WSRSAME || REG_WSRALL
@@REG_MNEM@ ^= $%cREG_VALUE$;
    $$END$
    $$IFN$ REG_WSRSAME &! REG_WSRALL
UserVar = @@REG_MNEM@;
wsr = $%cWSR_WRITE$;
@@REG_MNEM@ = UserVar ^ $%cREG_VALUE$;
    $$END$
  $$END$
$$END$
##80C196K? TESTZ# 500
##80C19? TESTZ# 500
$$IFSTR$ REG_MNEM "CCR" |STR "BAUD_RATE" |STR "WATCHDOG"
  $$IFSTR$ REG_MNEM "CCR"
Unsupported Operation:
@@REG_MNEM@ register is a read-only register.
  $$END$
  $$IFSTR$ REG_MNEM "BAUD_RATE"
Unsupported Operation:
@@REG_MNEM@ register is a write-only register.
  $$END$
  $$IFSTR$ REG_MNEM "WATCHDOG"
Unsupported Operation:
@@REG_MNEM@ register is a write-only register.
  $$END$
$$END$
$$ELSE$
  $$IFN$ REG_WSRALL
wsr = $%cWSR_READ$;
  $$END$
if(!(@@REG_MNEM@ & $%cREG_VALUE$))
{
  /* User Code */
}
$$END$
##80C196K? TESTNZ# 500
##80C19? TESTNZ# 500
$$IFSTR$ REG_MNEM "CCR" |STR "BAUD_RATE" |STR "WATCHDOG"
  $$IFSTR$ REG_MNEM "CCR"
Unsupported Operation:
@@REG_MNEM@ register is a read-only register.
  $$END$
  $$IFSTR$ REG_MNEM "BAUD_RATE"
Unsupported Operation:
@@REG_MNEM@ register is a write-only register.
  $$END$
  $$IFSTR$ REG_MNEM "WATCHDOG"
Unsupported Operation:
@@REG_MNEM@ register is a write-only register.
  $$END$
$$END$
$$ELSE$
  $$IFN$ REG_WSRALL
wsr = $%cWSR_READ$;
  $$END$
if(@@REG_MNEM@ & $%cREG_VALUE$)
{
  /* User Code */
}
$$END$
##80C198 AD#
##80C196KB AD#
##80C196KC AD#
##80C196KD AD#
$$ifp$ 80C198 || 80C194 || 80C196KB
#pragma model(kb)
$$end$
$$ifp$ 80C196KC || 80C196KD
#pragma model(kc)
$$end$
#include <80c196kd.h>


#define  ATOD_BUSY            (ad_result & 0x08)
#define  GO_NOW               0x08
#define  GO_EPA               0x00
#define  TEN_BIT_MODE         0x00
#define  EIGHT_BIT_MODE       0x10
$$ifp$ 80C198 || 80C194 || 80C196KB
#define  AD_SPEED             4
$$end$
$$ifp$ 80C196KC || 80C196KD
#define  AD_COMPAT            3
  $$ifn$ IOC2.3
#define  AD_SPEED             4
  $$end$
$$end$
#define  AD_INT               1
  
void init_atod_converter(void)
{
/* 
* A/D conversion configuration:
$$ifp$ 80C198 || 80C194 || 80C196KB
*    speed           = $%tioc2.4$fast$normal$
$$end$
*    interrupt       = $%tINT_MASK.1$enabled$disabled$ 
$$ifp$ 80C198
*    channel         = $%4AD_COMMAND.0-2$4$5$6$7$
$$end$
$$ifnp$ 80C198
*    channel         = $$AD_COMMAND.0-2$
$$end$
*    start time      = $%TAD_COMMAND.3$started immediately$triggered by the HSO$
$$ifp$ 80C198 || 80C194 || 80C196KB
*    mode            = $%tAD_COMMAND.4$8-bit$10-bit$
$$end$
$$ifp$ 80C196KC || 80C196KD
*    mode            = $%tioc2.3$configurable$compat$
   $$ifn$ IOC2.3
*    speed           = $%tioc2.4$fast$normal$
   $$end$
   $$if$ IOC2.3
*    sample time     = @@SAMP_TM@ microseconds
*    conversion time = @@CONV_TM@ microseconds
   $$end$
$$end$
*/

$$ifp$ 80C196KC || 80C196KD
  _$%tIOC2.3$Set$Clr$SFR_bit (ioc2, AD_COMPAT);
  $$ifn$ IOC2.3
  _$%tIOC2.4$Set$Clr$SFR_bit (ioc2, AD_SPEED);
  $$end$
  $$if$ IOC2.3
  _WriteSFR   (ad_time, 0x$$AD_TIME$);
  $$end$
$$end$
$$ifp$ 80C198 || 80C194 || 80C196KB
  _$%tIOC2.4$Set$Clr$SFR_bit (ioc2, AD_SPEED);
$$end$
  _$%tINT_MASK.1$Set$Clr$SFR_bit (int_mask, AD_INT);
$$ifp$ 80C198
  _WriteSFR   (ad_command, $%cAD_COMMAND+4$);
$$end$
$$ifnp$ 80C198
  _WriteSFR   (ad_command, $%cAD_COMMAND$);
$$end$
}
$$ifn$ INT_MASK.1
/*   convert_atod performs an atod conversion and.  This routine 
     waits until the atod busy bit is cleared before and after the 
     conversion. Interrupts should be disabled and the ATOD 
     should be initialized prior to calling this routine.     */

$%tAD_COMMAND.3$unsigned int$void$ convert_atod(unsigned char channel)
{
 wsr = 0;
 while(ATOD_BUSY);
 ad_command =  channel | $%tAD_COMMAND.3$GO_NOW$GO_EPA$ | $%tAD_COMMAND.4$EIGHT$TEN$_BIT_MODE;
     $$if$ AD_COMMAND.3
 zero_reg=zero_reg+zero_reg;     /*  needed for 4 state delay  */
 zero_reg=zero_reg+zero_reg;     /*  needed for 4 state delay  */
 while(ATOD_BUSY);
          $$ifn$ AD_COMMAND.4
 return((ad_result >> 6));
          $$end$
          $$if$  AD_COMMAND.4
 return(ad_result_hi);
          $$end$
     $$end$
}
$$end$

void main(void)
{
$$ifn$ INT_MASK.1 && AD_COMMAND.3
unsigned int result;
$$end$
     /*   Initialize the atod unit  */
 init_atod_converter();
$$if$ INT_MASK.1
 enable();
 ad_command = $%TAD_COMMAND.3$GO_NOW$GO_EPA$ | 0x0$$AD_COMMAND.0-2$ /* channel number */ |
              $%TAD_COMMAND.4$EIGHT_BIT_MODE$TEN_BIT_MODE$;

 while(1);     /*  Wait around for the interrupt  */
$$end$
$$ifn$ INT_MASK.1 && AD_COMMAND.3
 result = convert_atod(0x0$$AD_COMMAND.0-2$);
 while(1);
$$end$
$$ifn$ INT_MASK.1 &! AD_COMMAND.3
 convert_atod(0x0$$AD_COMMAND.0-2$);
 while(1);   /*   wait for epa to generate atod.  The result
                  should be serviced by an interrupt.  */
$$end$
}
$$if$ INT_MASK.1
#pragma interrupt(atod_interrupt=0x01)

/*   The atod_interrupt routine will be vectored to if interrupts
     are enabled and a atod conversion has completed.  */

void atod_interrupt()
{
     $$ifn$  AD_COMMAND.4
 unsigned int result;  /* used for temporary storage  */
 result = (ad_result >> 6);

/*  result can now be stored or acted upon by user's code  */
     $$end$
     $$if$ AD_COMMAND.4
 unsigned char result;  /* used for temporary storage  */
 result = (ad_result_hi);

/*  result can now be stored or acted upon by user's code  */
     $$end$
}
$$end$
##80C194 PWM#
##80C198 PWM#
##80C196KB PWM#
##80C196KC PWM0#
##80C196KD PWM0#
##80C196KC PWM1#
##80C196KD PWM1#
##80C196KC PWM2#
##80C196KD PWM2#
$$ifp$ 80C198 || 80C194 || 80C196KB
#pragma model(kb)
$$end$
$$ifp$ 80C196KC || 80C196KD
#pragma model(kc)
$$end$
#include <80c196kd.h>

$$if$ (PWM_NUMBER == 0)
#define   PWM$$PWM_NUMBER$_ENABLE     0
$$end$
$$if$ (PWM_NUMBER == 1)
#define   PWM$$PWM_NUMBER$_ENABLE     2
$$end$
$$if$ (PWM_NUMBER == 2)
#define   PWM$$PWM_NUMBER$_ENABLE     3
$$end$
#define   PWM_PRESCALE    2

void init_pwm$$PWM_NUMBER$(void)
{
/*
* PWM$$PWM_NUMBER$ configuration:
*   prescaler mode  = divide by $%tIOC2.2$2$1$
$$if$ (PWM_NUMBER == 0)
*   PWM output      = $%tIOC1.0$enabled$disabled$
$$end$
$$if$ (PWM_NUMBER == 1)
*   PWM output      = $%tIOC3.2$enabled$disabled$
$$end$
$$if$ (PWM_NUMBER == 2)
*   PWM output      = $%tIOC3.3$enabled$disabled$
$$end$
*   PWM duty cycle  = @@PWM_DUTY_CYCLE@ %
*
* pwm$$PWM_NUMBER$_control = 256 * (Duty Cycle) / 100
*/

  _$%tIOC2.2$Set$Clr$SFR_bit (ioc2, PWM_PRESCALE);
$$if$ (PWM_NUMBER == 0)
  _WriteSFR   (pwm$$PWM_NUMBER$_control, 0x$$PWM0_CONTROL$);
  _$%tIOC1.0$Set$Clr$SFR_bit (ioc1, PWM$$PWM_NUMBER$_ENABLE);
$$end$
$$if$ (PWM_NUMBER == 1)
  _WriteSFR   (pwm$$PWM_NUMBER$_control, 0x$$PWM1_CONTROL$);
  _$%tIOC3.2$Set$Clr$SFR_bit (ioc3, PWM$$PWM_NUMBER$_ENABLE);
$$end$
$$if$ (PWM_NUMBER == 2)
  _WriteSFR   (pwm$$PWM_NUMBER$_control, 0x$$PWM2_CONTROL$);
  _$%tIOC3.3$Set$Clr$SFR_bit (ioc3, PWM$$PWM_NUMBER$_ENABLE);
$$end$
}
void main(void)
{
  init_pwm$$PWM_NUMBER$();
  while(1);
}  
##80C194 Serial#
##80C198 Serial#
##80C196KB Serial#
##80C196KC Serial#
##80C196KD Serial#
$$ifp$ 80C198 || 80C194 || 80C196KB
#pragma model(kb)
$$end$
$$ifp$ 80C196KC || 80C196KD
#pragma model(kc)
$$end$
#include <80c196kd.h>

#define   SP_MODE0           0x00
#define   SP_MODE1           0x01
#define   SP_MODE2           0x02
#define   SP_MODE3           0x03
#define   REC_ENABLE         0x08
#define   REC_DISABLE        0x00
#define   TXD_ENABLE_BIT     0x05         
#define   EVEN_PARITY        0x08
#define   ODD_PARITY         0x28
#define   NO_PARITY          0x00
#define   SET_BIT_8          0x04
#define   SP_INTERNAL_CLK    0x8000
#define   SP_EXTERNAL_CLK    0x0000
#define   TXD_INTERRUPT      0x00
#define   RXD_INTERRUPT      0x01
#define   SERIAL_INT         0x06
#define   TI_BIT             0x05
#define   RI_BIT             0x06
#define   FE_BIT             0x04
#define   OE_BIT             0x02
#define   RPE_BIT            0x07
#define   RB8_BIT            0x07
#define   TXE_BIT            0x03

/****************************************************************************/
/*                                                                          */
/* Usefull bit macros.                                                      */
/*                                                                          */
/****************************************************************************/

#define   checkbit(var,bit)  (var & (0x01 << (bit)))
#define   setbit(var,bit)    (var |= (0x01 << (bit)))
#define   clrbit(var,bit)    (var &= (~(0x01 << (bit))))

static unsigned char sp_status_image;
$$ifn$ INT_MASK1.1 |! INT_MASK1.0 |! INT_MASK.6
     $$ifn$ INT_MASK1.0 &! INT_MASK.6 && IOC1.5
void putchar(unsigned int transmit_byte)
{
 while(!checkbit((sp_status_image |= sp_stat), TXE_BIT));

          $$if$ SP_CON.4
/*   If bit 8 needs to be set, then the following line needs to
     be inserted:
     _SetSFR_bit(sp_con, SET_BIT_8);   */
          $$end$
 sbuf = transmit_byte;
 clrbit(sp_status_image, TXE_BIT);
}
     $$end$
     $$ifn$ INT_MASK1.1 &! INT_MASK.6 && SP_CON.3
unsigned char getchar()
{
 while(!checkbit((sp_status_image |= sp_stat), RI_BIT));
 if(checkbit(sp_status_image, FE_BIT))
     {
     ;    /*  User code for framing error  */
     clrbit(sp_status_image, FE_BIT);
     }   
 if(checkbit(sp_status_image, OE_BIT))
     {
     ;    /*  User code for overrun error  */
     clrbit(sp_status_image, OE_BIT);
     }   
          $$if$ SP_CON.2
 if(checkbit(sp_status_image, RPE_BIT))
     {
     ;    /*  User code for Parity error  */
     clrbit(sp_status_image, RPE_BIT);
     }   
          $$end$
          $$if$ SP_CON.4
 if(checkbit(sp_status_image, RB8_BIT))
     {
     ;    /*  User code for Receiving BIT 8 */
     clrbit(sp_status_image, RB8_BIT);
     }   
          $$end$
 clrbit(sp_status_image, RI_BIT);
 return sbuf;
}
     $$end$
$$end$
$$if$ INT_MASK1.0-1 || INT_MASK.6
     $$if$ INT_MASK1.1

#pragma interrupt(receive=25)
     $$end$