?? 80c196kd.h
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/*
* Copyright (c) 1995, Intel Corporation
*
* $Workfile: 80c196kd.h $
* $Revision: 1.1 $
* $Modtime: Mar 22 1995 16:59:32 $
*
* Purpose:
*
*
*
*
*
* Compiler:
*
* Ext Packages:
*
*
*
*/
/************************************************************************
; 80C196.INC - DEFINITION OF SYMBOLIC NAMES FOR THE I/O REGISTERS OF THE
; 80C196
;***********************************************************************/
#ifndef _HOLDEN
#define _HOLDEN 0x00 /*Set to 0x80 if HOLD/HOLDA used, 0 otherwise */
#endif
/* Register Naming used by the Intel iC-96 compiler */
extern volatile register unsigned short r0; /* at 0x00 */
extern volatile register unsigned char ad_command; /* at 0x02 */
extern volatile register unsigned short ad_result; /* at 0x02 */
extern volatile register unsigned char ad_result_lo;/* at 0x02 */
extern volatile register unsigned char ad_result_hi;/* at 0x03 */
extern volatile register unsigned char ad_time; /* at 0x03 */
extern volatile register unsigned char hsi_mode; /* at 0x03 */
extern volatile register unsigned short hso_time; /* at 0x04 */
extern volatile register unsigned short hsi_time; /* at 0x04 */
extern volatile register unsigned short ptssel; /* at 0x04 */
extern volatile register unsigned char hso_command; /* at 0x06 */
extern volatile register unsigned char hsi_status; /* at 0x06 */
extern volatile register unsigned short ptssrv; /* at 0x06 */
extern volatile register unsigned char sbuf; /* at 0x07 */
extern volatile register unsigned char int_mask; /* at 0x08 */
extern volatile register unsigned char int_pending; /* at 0x09 */
extern volatile register unsigned char watchdog; /* at 0x0a */
extern volatile register unsigned short timer1; /* at 0x0a */
extern volatile register unsigned char ioc2; /* at 0x0b */
extern volatile register unsigned short timer2; /* at 0x0c */
extern volatile register unsigned short t2capture; /* at 0x0c */
extern volatile register unsigned char t2control; /* at 0x0c */
extern volatile register unsigned char baud_rate; /* at 0x0e */
extern volatile register unsigned char ioport0; /* at 0x0e */
extern volatile register unsigned char ioport1; /* at 0x0f */
extern volatile register unsigned char ioport2; /* at 0x10 */
extern volatile register unsigned char sp_con; /* at 0x11 */
extern volatile register unsigned char sp_stat; /* at 0x11 */
extern volatile register unsigned char ipend1; /* at 0x12 */
extern volatile register unsigned char imask1; /* at 0x13 */
extern volatile register unsigned char wsr; /* at 0x14 */
extern volatile register unsigned char ioc0; /* at 0x15 */
extern volatile register unsigned char ios0; /* at 0x15 */
extern volatile register unsigned char ioc1; /* at 0x16 */
extern volatile register unsigned char ios1; /* at 0x16 */
extern volatile register unsigned char pwm1_control;/* at 0x16 */
extern volatile register unsigned char pwm2_control;/* at 0x17 */
extern volatile register unsigned char pwm_control; /* at 0x17 */
extern volatile register unsigned char ios2; /* at 0x17 */
/* Added for naming conflicts */
#define int_pend int_pending
#define ioc3 t2control
#define zero_reg r0
#define int_pend1 ipend1
#define int_mask1 imask1
#define pwm0_control pwm_control
/* These defines are used to assign the read/write windows to each register */
#define WIN0 0x0
#define WR_WIN_MASK 0x0f
#define RD_WIN_MASK 0x4
#define READ_WIN0 0x00
#define READ_WIN1 0x10
#define READ_WIN15 0xf0
#define WRITE_WIN0 0x00
#define WRITE_WIN1 0x01
#define WRITE_WIN15 0x0f
#define READ_WRITE_ANY 0x55
#define RD_WR_ANY READ_WRITE_ANY
#define zero_reg_w READ_WRITE_ANY
#define ad_command_w READ_WIN15 + WRITE_WIN0
#define ad_result_w READ_WIN0 + WRITE_WIN15
#define hsi_mode_w READ_WIN15 + WRITE_WIN0
#define hso_time_w READ_WIN15 + WRITE_WIN0
#define hsi_time_w READ_WIN0 + WRITE_WIN15
#define hso_command_w READ_WIN15 + WRITE_WIN0
#define hsi_status_w READ_WIN0 + WRITE_WIN15
#define sbuf_w READ_WIN0 + WRITE_WIN15
#define int_mask_w READ_WRITE_ANY
#define int_pend_w READ_WRITE_ANY
#define timer1_w READ_WIN0 + WRITE_WIN15
#define timer2_w READ_WIN0 + WRITE_WIN15
#define baud_rate_w WRITE_WIN0
#define ioport0_w READ_WIN0
#define ioport1_w READ_WIN0 + WRITE_WIN0
#define ioport2_w READ_WIN0 + WRITE_WIN0
#define sp_con_w READ_WIN15 + WRITE_WIN0
#define sp_stat_w READ_WIN0 + WRITE_WIN15
#define ioc0_w READ_WIN15 + WRITE_WIN0
#define ios0_w READ_WIN0 + WRITE_WIN15
#define ioc1_w READ_WIN15 + WRITE_WIN0
#define ios1_w READ_WIN0 + WRITE_WIN15
#define pwm0_control_w READ_WIN15 + WRITE_WIN0
#define ioc2_w READ_WIN15 + WRITE_WIN0
#define ioc3_w READ_WIN1 + WRITE_WIN1
#define t2capture_w READ_WIN15 + WRITE_WIN15
#define int_pend1_w READ_WRITE_ANY
#define int_mask1_w READ_WRITE_ANY
#define wsr_w READ_WRITE_ANY
#define ios2_w READ_WIN0 + WRITE_WIN15
#define ad_time_w READ_WIN1 + WRITE_WIN1
#define ptssel_w READ_WIN1 + WRITE_WIN1
#define ptssrv_w READ_WIN1 + WRITE_WIN1
#define pwm1_control_w READ_WIN1 + WRITE_WIN1
#define pwm2_control_w READ_WIN1 + WRITE_WIN1
/* Added to account for naming conflicts */
#define int_pending_w int_pend_w
#define t2control_w ioc3_w
#define ad_result_lo_w ad_result_w
#define r0_w zero_reg_w
#define ipend1_w int_pend1_w
#define imask1_w int_mask1_w
#define pwm_control_w pwm0_control_w
/* Used by the macros */
extern register unsigned int tmpreg;
#define Concat(a,b) a ## b
/*------------------------------------------------------------------*/
#define _ReadSFR(Destination, SFR) \
if (Concat(SFR,_w) != RD_WR_ANY)\
{\
wsr = ((Concat(SFR,_w) >> RD_WIN_MASK) & 0xf) + _HOLDEN; \
}\
Destination = SFR;
/*------------------------------------------------------------------*/
#define _WriteSFR(SFR, Value) \
if (Concat(SFR,_w) != RD_WR_ANY)\
{\
wsr = (Concat(SFR,_w) & WR_WIN_MASK) + _HOLDEN; \
}\
SFR = Value;
/*------------------------------------------------------------------*/
#define _SetSFR_bit(SFR, BitNumber) \
if (Concat(SFR,_w) != RD_WR_ANY)\
{\
wsr = ((Concat(SFR,_w) >> RD_WIN_MASK) & 0xf) + _HOLDEN; \
}\
tmpreg = SFR | (1 << BitNumber); \
if ((Concat(SFR,_w) != RD_WR_ANY) || (Concat(SFR,_w) != Concat(SFR,_w)))\
{\
wsr = (Concat(SFR,_w) & WR_WIN_MASK) + _HOLDEN; \
}\
SFR = tmpreg;
/*------------------------------------------------------------------*/
#define _ClrSFR_bit(SFR, BitNumber) \
if (Concat(SFR,_w) != RD_WR_ANY)\
{\
wsr = ((Concat(SFR,_w) >> RD_WIN_MASK) & 0xf) + _HOLDEN; \
}\
tmpreg = SFR & (~(1 << BitNumber)); \
if ((Concat(SFR,_w) != RD_WR_ANY) || (Concat(SFR,_w) != Concat(SFR,_w)))\
{\
wsr = (Concat(SFR,_w) & WR_WIN_MASK) + _HOLDEN; \
}\
SFR = tmpreg;
/*------------------------------------------------------------------*/
#define _OrSFR(SFR, MaskValue) \
if (Concat(SFR,_w) != RD_WR_ANY)\
{\
wsr = ((Concat(SFR,_w) >> RD_WIN_MASK) & 0xf) + _HOLDEN; \
}\
tmpreg = SFR | MaskValue; \
if ((Concat(SFR,_w) != RD_WR_ANY) || (Concat(SFR,_w) != Concat(SFR,_w)))\
{\
wsr = (Concat(SFR,_w) & WR_WIN_MASK) + _HOLDEN; \
}\
SFR = tmpreg;
/*------------------------------------------------------------------*/
#define _AndSFR(SFR, MaskValue) \
if (Concat(SFR,_w) != RD_WR_ANY)\
{\
wsr = ((Concat(SFR,_w) >> RD_WIN_MASK) & 0xf) + _HOLDEN; \
}\
tmpreg = SFR & MaskValue; \
if ((Concat(SFR,_w) != RD_WR_ANY) || (Concat(SFR,_w) != Concat(SFR,_w)))\
{\
wsr = (Concat(SFR,_w) & WR_WIN_MASK) + _HOLDEN; \
}\
SFR = tmpreg;
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