#PCA 80C151SX#
Programmable Counter Array\n
 - Measures periods, pulse widths, duty cycles, and phase differences\n
 - 16-bit timer/counter with 250-ns resolution at 16 MHz\n
 - Five high-speed, 16-bit modules\n
     Input capture: rising, falling, or both edges\n
     Output compare\n
     Pulse-width modulation\n
     Programmable 16-bit watchdog timer (module 4 only)\n
#Serial 80C151SX#
Serial Port\n
 - Full duplex\n
 - One synchronous and three asynchronous modes\n
 - Variable baud rate\n
 - Framing error detection\n
 - Multi-processor communications\n
 - Automatic address recognition\n
 - Interrupt on reception and transmission of data byte\n
#Clock 80C151SX#
Clock\n
 - 8XC151SX operates at 0 - 16 MHz\n
#Timer 80C151SX#
Timer/Counters\n
 - Three 16-bit units: timer 0, timer 1, timer 2\n
 - Timer or counter operation\n
 - Internal or external clocking\n
\n
 - Timer 0 and timer 1 modes:\n
     13-bit timer or counter\n
     16-bit timer or counter\n
     8-bit auto-reload timer or counter\n
     Two 8-bit timers\n
\n
 - Timer 2 modes:\n
     Auto-reload (up or up/down counter/timer)\n
     Independent event capture\n
     Baud rate generator\n
     Programmable clock-out at 50% duty cycle\n
#CPU 80C151SX#
Central Processing Unit\n
 - High-performance CPU\n
 - Linear address space\n
 - Accumulator-based architecture\n
 - Standard MCS(R) 51 instruction set\n
#WDT 80C151SX#
Watchdog Timer\n
 - 14-bit timer\n
 - Allows recovery from system upsets\n
 - Increases system reliability\n
 - One-time enabled\n
 - Resets chip on overflow\n
#DATA 80C151SX#
RAM\n
 - 256-byte on-chip general-purpose data RAM,\n
    accessible by direct addressing\n
#CODE 80C151SX#
EPROM/OTPROM/ROM\n
 - 8XC151SA 8-Kbyte on-chip program memory\n
 - 8XC151SB 16-Kbyte on-chip program memory\n
 - Romless version available\n
#IO 80C151SX#
I/O Ports\n
 - 32 bidirectional I/O pins\n
#BU 80C151SX#
Bus Interface Unit\n
 - 64 Kbyte addressability\n
 - 16 bit external address bus\n
#IU 80C151SX#
Interrupt Control Unit\n
 - Seven interrupt sources\n
 - Four priority levels\n
#PM 80C151SX#
Power Management\n
 Idle mode\n
    - SFRs and on-chip data RAM retain their values\n
    - Peripherals continue to operate\n
    - Any enabled interrupt awakens the chip\n
\n
Powerdown mode\n
    - SFRs and on-chip data RAM retain their values\n
    - Peripherals stop operation\n
    - Any enabled external interrupt awakens the chip\n
    - Vcc can be reduced as low as 2 V\n
\n
 Power off flag\n
    - Used to distinguish between\n
      'cold-start' reset and 'warm-start' reset\n
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