<PE_PROJECT_SETTINGS_DOCUMENTATION>
  <PE_product_version v="version 3.04 for Freescale HC(S)08/RS08/CFV1"/>
  <PE_core_version v="Processor Expert Version 0419"/>

  <CPU_Bean name="Cpu" type="MC9RS08LE4_28">
    <Enabled v="Y"/>

    <Properties>
      <Bean_name v="Cpu"/>
      <CPU_type v="MC9RS08LE4CPC"/>
      <list name="Shared Internal properties" v="1">
      </list>
      <list name="Shared ICS module settings" v="1">
        <group name="Clock settings">
          <group name="Internal clock">
            <Internal_oscillator_frequency__kHz_ v="32.700000000000"/>
            <Internal_ref__clock_for_peripherals v="Enabled"/>
            <boolgroup name="Initialize trim value" v="yes">
              <Trim_value_address v="16378"/>
              <Fine_trim_value_address v="16379"/>
            </boolgroup>
          </group>
          <boolgroup name="External clock" v="Disabled" />
          <group name="Low-power modes settings">
            <boolgroup name="STOP instruction enabled" v="yes">
              <Internal_clock_in_stop_mode v="Enabled"/>
              <External_clock_in_stop_mode v="Disabled"/>
            </boolgroup>
          </group>
        </group>
      </list>
      <list name="Shared internal resource mapping" v="1">
        <group name="Internal resource mapping">
          <group name="Reset vector">
            <Address v="16381"/>
            <Size v="3"/>
          </group>
        </group>
      </list>
      <group name="Internal peripherals">
        <list name="Shared ACMP settings" v="1">
          <group name="ACMP">
            <Internal_bandgap_buffer v="Disabled"/>
          </group>
        </list>
        <list name="Shared BDM settings" v="1">
          <boolgroup name="BDM pin support" v="Enabled">
            <BDM_pin v="PTB1_BKGD_MS"/>
            <BDM_pin_signal v=""/>
          </boolgroup>
        </list>
        <list name="Shared FLASH settings" v="1">
          <group name="FLASH">
            <Security_state v="Disabled"/>
          </group>
        </list>
        <list name="Internal Peripherals IO" v="1">
          <group name="I/O module">
            <list name="Shared Unused I/O" v="1">
              <enumgroup name="Initialize unused I/O pins" v="no initialization">
              </enumgroup>
            </list>
            <group name="PORT A">
              <Slew_rate_control_for_PTA0 v="no"/>
              <Slew_rate_control_for_PTA1 v="no"/>
              <Slew_rate_control_for_PTA2 v="no"/>
              <Slew_rate_control_for_PTA3 v="no"/>
              <Slew_rate_control_for_PTA4 v="no"/>
              <Slew_rate_control_for_PTA5 v="no"/>
              <Slew_rate_control_for_PTA6 v="no"/>
              <Slew_rate_control_for_PTA7 v="no"/>
              <Drive_strength_for_PTA0 v="High"/>
              <Drive_strength_for_PTA1 v="High"/>
              <Drive_strength_for_PTA2 v="High"/>
              <Drive_strength_for_PTA3 v="High"/>
              <Drive_strength_for_PTA4 v="High"/>
              <Drive_strength_for_PTA5 v="High"/>
              <Drive_strength_for_PTA6 v="High"/>
              <Drive_strength_for_PTA7 v="High"/>
            </group>
            <group name="PORT B">
              <Slew_rate_control_for_PTB1 v="no"/>
              <Slew_rate_control_for_PTB2 v="no"/>
              <Slew_rate_control_for_PTB3 v="no"/>
              <Slew_rate_control_for_PTB4 v="no"/>
              <Slew_rate_control_for_PTB5 v="no"/>
              <Slew_rate_control_for_PTB6 v="no"/>
              <Slew_rate_control_for_PTB7 v="no"/>
              <Drive_strength_for_PTB1 v="High"/>
              <Drive_strength_for_PTB2 v="High"/>
              <Drive_strength_for_PTB3 v="High"/>
              <Drive_strength_for_PTB4 v="High"/>
              <Drive_strength_for_PTB5 v="High"/>
              <Drive_strength_for_PTB6 v="High"/>
              <Drive_strength_for_PTB7 v="High"/>
            </group>
            <group name="PORT C">
              <Slew_rate_control_for_PTC0 v="no"/>
              <Slew_rate_control_for_PTC1 v="no"/>
              <Drive_strength_for_PTC0 v="High"/>
              <Drive_strength_for_PTC1 v="High"/>
            </group>
            <group name="PORT D">
              <Slew_rate_control_for_PTD0 v="no"/>
              <Slew_rate_control_for_PTD1 v="no"/>
              <Slew_rate_control_for_PTD2 v="no"/>
              <Slew_rate_control_for_PTD3 v="no"/>
              <Slew_rate_control_for_PTD4 v="no"/>
              <Slew_rate_control_for_PTD5 v="no"/>
              <Slew_rate_control_for_PTD6 v="no"/>
              <Slew_rate_control_for_PTD7 v="no"/>
              <Drive_strength_for_PTD0 v="High"/>
              <Drive_strength_for_PTD1 v="High"/>
              <Drive_strength_for_PTD2 v="High"/>
              <Drive_strength_for_PTD3 v="High"/>
              <Drive_strength_for_PTD4 v="High"/>
              <Drive_strength_for_PTD5 v="High"/>
              <Drive_strength_for_PTD6 v="High"/>
              <Drive_strength_for_PTD7 v="High"/>
            </group>
          </group>
        </list>
        <list name="Shared LVD settings" v="1">
          <boolgroup name="LVD module" v="Enabled">
            <LVD_operation v="Interrupt"/>
            <Enable_in_stop_mode v="no"/>
          </boolgroup>
        </list>
        <list name="Shared TMP modules setting" v="1">
        </list>
        <list name="Shared Reset pin setting" v="1">
          <boolgroup name="Reset pin support" v="Disabled" />
        </list>
      </group>
      <list name="Shared ICSv1 speed mode settings" v="1">
        <group name="Enabled speed modes">
          <boolgroup name="High speed mode" v="Enabled">
            <High_speed_clock v="Internal Clock"/>
            <Bus_freq__divider v="Auto select"/>
            <Internal_bus_clock v="1.046400000000"/>
            <Fixed_frequency_clock__MHz_ v="0.01635"/>
            <enumgroup name="FLL mode" v="Engaged">
              <Ref_clock_source v="Internal Clock"/>
              <Ref__clock_source_freq___MHz_ v="0.032700000000"/>
              <Ref__clock_divider v="1"/>
              <Divided_ref_clock_freq___MHz_ v="0.032700000000"/>
              <FLL_output_clock_freq___MHz_ v="16.742400000000"/>
            </enumgroup>
          </boolgroup>
          <boolgroup name="Low speed mode" v="Disabled" />
          <boolgroup name="Slow speed mode" v="Disabled" />
        </group>
      </list>
    </Properties>

    <Methods>
      <list name="SharedCpuMethods" v="1">
        <SetHighSpeed v="don&apos;t generate code"/>
        <SetLowSpeed v="don&apos;t generate code"/>
        <SetSlowSpeed v="don&apos;t generate code"/>
        <GetSpeedMode v="don&apos;t generate code"/>
        <GetResetSource v="don&apos;t generate code"/>
        <SetWaitMode v="generate code"/>
        <SetStopMode v="don&apos;t generate code"/>
        <GetLowVoltageFlag v="generate code"/>
        <ClearLowVoltageFlag v="generate code"/>
        <GetIdentification v="don&apos;t generate code"/>
        <Delay100US v="generate code"/>
      </list>
    </Methods>

    <Events>
      <Event_module_name v="Events"/>
      <event name="OnReset" v="don&apos;t generate code" />
    </Events>
    <Compiler v="CodeWarrior RS08 C Compiler"/>

    <CompilerProperties>
      <Compiler v="CodeWarrior RS08 C Compiler"/>
      <Generate_macros v="yes"/>
      <group name="User initialization">
        <User_data_declarations>
        </User_data_declarations>
        <User_code_before_PE_initialization>
        </User_code_before_PE_initialization>
        <User_code_after_PE_initialization>
        </User_code_after_PE_initialization>
      </group>
      <boolgroup name="Generate PRM file" v="yes">
        <Set_memory_areas_default v="Click to set default &gt;"/>
        <list name="ROM/RAM Areas" v="5">
          <group name="Memory Area0">
            <boolgroup name="ROM/RAM Area" v="Enabled">
              <Name v="RESERVED_RAM"/>
              <Address v="0"/>
              <Size v="5"/>
              <Qualifier v="NO_INIT"/>
            </boolgroup>
          </group>
          <group name="Memory Area1">
            <boolgroup name="ROM/RAM Area" v="Enabled">
              <Name v="TINY_RAM"/>
              <Address v="5"/>
              <Size v="9"/>
              <Qualifier v="READ_WRITE"/>
            </boolgroup>
          </group>
          <group name="Memory Area2">
            <boolgroup name="ROM/RAM Area" v="Enabled">
              <Name v="RAM"/>
              <Address v="80"/>
              <Size v="112"/>
              <Qualifier v="READ_WRITE"/>
            </boolgroup>
          </group>
          <group name="Memory Area3">
            <boolgroup name="ROM/RAM Area" v="Enabled">
              <Name v="ROM"/>
              <Address v="12288"/>
              <Size v="4090"/>
              <Qualifier v="READ_ONLY"/>
            </boolgroup>
          </group>
          <group name="Memory Area4">
            <boolgroup name="ROM/RAM Area" v="Disabled" />
          </group>
        </list>
      </boolgroup>
    </CompilerProperties>
  </CPU_Bean>

  <Bean name="LCD1" type="Init_LCD">
    <Enabled v="Y"/>

    <Properties>
      <Bean_name v="LCD1"/>
      <Device v="LCD"/>
      <group name="Settings">
        <group name="Clock settings">
          <Clock_source_select v="Alternate clock source"/>
          <Base_clock_prescaler v="7"/>
          <LCD_module_clock v="32.7 kHz"/>
          <Base_clock v="36.495 Hz"/>
          <Charge_pump_clock_adjust v="Intermediate (faster) clock"/>
          <Charge_pump_clock v="2.725 kHz"/>
          <Blink_rate_bits_value v="0"/>
          <Blink_rate v="7.983 Hz"/>
          <Display_mode v="1 backplane"/>
          <Duty v="1/1"/>
          <Frame_frequency v="36.495 Hz"/>
        </group>
        <Stop_in_Wait_mode v="no"/>
        <Stop_in_Stop_mode v="no"/>
        <Full_complementary_drive v="Disabled"/>
        <Voltage_supply_control v="Drive VLL3 from Vdd internally"/>
        <Blink_mode_select v="Alternate Display"/>
      </group>
      <group name="Pins">
        <list name="Frontplane pins" v="18">
          <group name="Frontplane pin0">
            <Frontplane_pin v="PTB5_ADP3_LCD18"/>
            <Frontplane_pin_signal v="A1"/>
          </group>
          <group name="Frontplane pin1">